Semiconductor device manufacturing: process – Chemical etching
Reexamination Certificate
2000-06-30
2002-06-25
Nguyen, Viet Q. (Department: 2818)
Semiconductor device manufacturing: process
Chemical etching
C438S695000
Reexamination Certificate
active
06410437
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor manufacture. More particularly, the present invention teaches a novel methodology for forming dual damascene structures in semiconductor wafers including at least one low-K dielectric layer.
DESCRIPTION OF THE RELATED ART
Integrated circuits use dielectric layers, which have typically been formed from silicon dioxide, SiO
2
, to insulate conductive lines on various layers of a semiconductor structure. As semiconductor circuits become faster and more compact, operating frequencies increase and the distances between the conductive lines within the semiconductor device decrease. This introduces an increased level of coupling capacitance to the circuit, which has the drawback of slowing the operation of the semiconductor device. Therefore, it has become important to use dielectric layers that are capable of effectively insulating conductive lines against such increasing coupling capacitance levels.
In general, the coupling capacitance in an integrated circuit is directly proportional to the dielectric constant, K, of the material used to form the dielectric layers. As noted above, the dielectric layers in conventional integrated circuits have traditionally been formed Of SiO
2
, which has a dielectric constant of about 4.0. As a consequence of the increasing line densities and operating frequencies in semiconductor devices, dielectric layers formed of SiO
2
may not effectively insulate the conductive lines to the extent required to avoid increased coupling capacitance levels.
In an effort to reduce the coupling capacitance levels in integrated circuits, the semiconductor industry has engaged in research to develop materials having a dielectric constant lower than that of SiO
2
, which materials are suitable for use in forming the dielectric layers in integrated circuits. To date, a number of promising materials, which are sometimes referred to as “low-K materials”, have been developed. Many of these new dielectrics are organic compounds.
One interesting class of organic low-K materials are compounds including organosilicate glass. By way of example, but not limitation such organosilicate dielectrics include CORAL™ from Novellus of San Jose, Calif.; Black Diamond™ from Applied Materials of Santa Clara, Calif.; and Sumika Film ™ available from Sumitomo Chemical America, Inc., Santa Clara, Calif.
During semiconductor wafer processing, features of the semiconductor device have been defined in the wafer using well-known patterning and etching processes. In these processes a photo resist material may be deposited on the wafer and may then be exposed to light filtered by a reticle. The reticle may be a glass plate that is patterned with exemplary feature geometries that block light from propagating through the reticle.
The development of an effective etching process for an organosilicate glass low-K film such as CORAL™ should take into account several criteria including etch rate, profile control, selectivity to underlying materials as well as critical dimension (CD) control. The etching of low-K dielectric materials was at first approached as if a silicon-based dielectric were being etched. This has not proven particularly effective, as with organic low-K films the chemistries and processes needed to effectively etch the material are substantially different than those for traditional silicon or silicon oxide etching. This has proven even more problematic for the etching of organosilicate glass low-K films.
Organosilicate glass low-K films are often etched using etchant gas flows of similar chemical composition to other materials used in the semiconductor manufacturing process. This can render the manufacture of such devices difficult. One structure which has proven difficult to implement in wafers with small feature sizes and high feature densities while implementing organosilicate glass low-K dielectric films, is a dual damascene structure. Such dual damascene structures include an interconnect layer and one or more vias to provide electrical connectivity to an underlying electrically conductive feature, especially a metalized feature.
What is desired is a methodology for forming a dual damascene etch structure within a wafer, where at least part of the damascene is formed within a low-K organosilicate glass dielectric, while reliably maintaining feature size and density.
What is finally desirable is a methodology which can be implemented using existing equipment and chemistries, while reliably forming the dual damascene within the organosilicate glass low-K dielectric.
These and other advantages of the present invention will become apparent upon reading the following detailed descriptions and studying the various figures of the Drawing.
SUMMARY OF THE INVENTION
In order to accomplish the desired advantages, previously discussed, the present invention teaches a method for forming a dual damascene etch structure in a wafer, where the wafer includes at least one layer of organosilicate glass dielectric. The novel method taught by the present invention includes the steps etching through a major portion of the organosilicate glass dielectric utilizing a first, low selectivity etchant. This etching step leaves a very small remainder portion of the organosilicate glass dielectric atop the barrier layer. Thereafter, the present invention uses a second, low selectivity etchant to etch away the remainder portion of the organosilicate glass dielectric.
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patent: 6030901 (2000-02-01), Hopper et al.
patent: 6072227 (2000-06-01), Yau et al.
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patent: WO0003432 (2000-01-01), None
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Morey, et al., “Etch challenges of low-&kgr; dielectrics”, Jun. 1999, Solid State Technology, pp. 71-78.
Ellingboe, et al., “Review of Low-&kgr; Dielectric Etching”, Sep., 1999, VMIC Conference, pp. 415-422.
PCT International Search Report, Date of Mailing Jan. 24, 2002.
Flanner Janet M.
Morey Ian
Lam Research Corporation
Nguyen Viet Q.
Nhu David
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