Method for estimating aggregate leakage of transistors

Details Method for estimating aggregate leakage of transistors Method for estimating aggregate leakage of transistors

2008-05-12

2009-02-03

Kik, Phallaka (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C703S002000, C703S016000

Reexamination Certificate

active

07487480

ABSTRACT:
A method of estimating a leakage for a plurality of transistors in an integrated circuit that accounts for narrow channel effects includes determining an expected total leaking transistor width for the collection; determining an expected total number of leaking transistors for the collection; determining an average width of a leaking transistor from the expected total leaking transistor width and expected total number of leaking transistors; estimating a leakage for a transistor of the average width; and determining the estimated leakage for the collection of transistors by multiplying the leakage for a transistor of the average width by the expected total number of leaking transistors for the collection.

REFERENCES:
patent: 2005/0034089 (2005-02-01), McGuffin et al.
patent: 2007/0070783 (2007-03-01), Lee
patent: 2007/0250797 (2007-10-01), Engel et al.
patent: 2008/0209371 (2008-08-01), Muraya et al.
Sathanur et al., “Efficient Computation of Discharge Current Upper Bounds for Clustered Sleep Transistor Sizing”, 2007 Design, Automation & Test in Europe Conference & Exhibition, Apr. 16-20, 2007, pp. 1-6.
Shi et al., “Sleep Transistor Design and Implementation—Simple Concepts Yet Changes to be Optimum”, 2006 International Symposium on VLSI Design, Automation and Test, Apr. 2006, pp. 1-4.

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