Method for error compensation and a memory control device...

Details Method for error compensation and a memory control device... Method for error compensation and a memory control device...

2006-04-25

2008-08-05

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Read/write circuit

Signals

C365S193000, C365S233100, C702S106000

Reexamination Certificate

active

07408821

ABSTRACT:
A memory control device and a memory control method are provided to compensate for additional delay subsequent to the change in environmental factors and to permit a smooth writing operation. The memory control device includes a controller that calculates a number of delay cells that are necessary to delay a system clock for one period as delay information, and a compensation unit that generates a compensation control signal by using the delay information calculated by the controller signal. The compensation unit compensates for an additional delay which is subsequent to a change in environmental factors such as voltage or temperature.

REFERENCES:
patent: 6400641 (2002-06-01), Manning
patent: 6985401 (2006-01-01), Jang et al.
patent: 7171321 (2007-01-01), Best
patent: 1492121 (2004-12-01), None
patent: 2005-078547 (2005-03-01), None
patent: 10-2003-0056811 (2003-07-01), None

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