Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-11-12
2002-09-10
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S234000
Reexamination Certificate
active
06448124
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of fabricating integrated circuits and, in particular to a method of forming field effect transistors (FETs) and bipolar devices on the same substrate. More specifically, the present invention provides an integration scheme that is capable of fabricating a base-after gate BiCMOS (i.e., bipolar device and complementary metal oxide semiconductor (CMOS) device) integrated circuit which solves the problems typically associated with prior art integration schemes.
BACKGROUND OF THE INVENTION
In the field of semiconductor device manufacturing, it is well known to fabricate BiCMOS integrated circuits using a so-called base-during gate process. Base-during gate processes are described, for example, in D. L. Harame, et al. “Si/SiGe Epitaxial—Base Transistors—Part I: Materials Physics and Circuits”, IEEE Trans. Elect. Devices, pp. 469-482, March 1995; D. L. Harame, et al., “Si/SiGe Epitaxial—Base Transistors—Part II: Process Integration and Analog Applications”, IEEE Trans. Elect. Devices, pp. 469-482, March 1995; and D. Ahlgren, et al., “A SiGe HBT BiCMOS Technology for Mixed Signal RF Applications”, Proc. of the 1997 BCTM, pp 95-197, 1997. In such base-during gate processes, the gate polysilicon is formed at the same time as the base epitaxial silicon is grown.
An alternative method of fabricating BiCMOS integrated circuits is to employ a base-after gate process. In this process, the gate polysilicon is formed before the base epitixial silicon is grown. Such a process is described, for example, in U.S. Pat. No. 5,665,615 to Anmo and 5,665,616 to Kimura, et al.
Several problems are evident in using such prior art processes. A first problem is controlling the base outdiffusion during CMOS source/drain (S/D) and lightly doped drain (LDD) anneals. A second problem is how to provide a high quality epitaxial surface for base growth; and a third problem is how to protect the CMOS device during bipolar device formation. When a base-after gate integration scheme is employed, the following two additional manufacturing requirements must be taken into consideration: First, FET spacer structures must not be produced on the bipolar devices; and secondly, bipolar films must not be left on the FET devices after fabricating the same.
In view of the aforementioned drawbacks with prior art integration schemes for BiCMOS fabrication, there is a continued need for developing a new and improved base-after gate integration process wherein all of the above-mentioned problems and requirements have been met.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a method of fabricating a BiCMOS integrated circuit in which the FETs and bipolar devices are fabricated on the same substrate.
Another object of the present invention is to provide a method of fabricating a BiCMOS integrated circuit using an integration scheme in which no thermal limitation is put on the CMOS device during bipolar device formation.
A still further object of the present invention is to provide a method in which a high quality surface for epitaxial base growth is provided.
A yet further object of the present invention is to provide a method of fabricating a BiCMOS device in which the CMOS devices are protected during bipolar device formation and vice versa.
An additional object of the present invention is to provide a method of fabricating a BiCMOS device in which bipolar films are not left on the FET devices. These and other objects and advantages are met by forming portions of bipolar devices on a substrate, protecting the portions with a protective layer while forming FET devices, and protecting the FET devices while forming other portions of the bipolar devices. Specifically, the method of the present invention comprises the steps of:
(a) forming a first portion of a bipolar device in first regions of a substrate;
(b) forming a first protective layer over said first regions to protect said first portion of said bipolar device;
(c) forming a field effect transistor device in second regions of said substrate;
(d) forming a second protective layer over said second regions of said substrate to protect said field effect transistor device;
(e) removing said first protective layer;
(f) forming a second portion of said bipolar device in said first regions of said substrate; and
(g) removing said second protective layer.
In one embodiment of the present invention, a portion of the second protective layer remains in;the structure covering a portion of said bipolar device. In other embodiments of the present invention, a portion of the first protective layer remains over the FET device or portions of the first and second protective layers remain in the structure after fabrication.
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Coolbaugh Douglas D.
Dunn James S.
Geiss Peter J.
Gray Peter B.
Harame David L.
Nguyen Tuan H.
Sabo William D.
Scully Scott Murphy & Presser
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