Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-01-26
2004-01-20
Ho, Hoai (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S341000
Reexamination Certificate
active
06680229
ABSTRACT:
TECHNICAL FIELD
The present invention is related generally to semiconductor processing, and more particularly to the selective formation of silicon during manufacture of a semiconductor device.
BACKGROUND OF THE INVENTION
During the formation of semiconductor integrated circuits, devices are formed in a semiconductor substrate and interconnected to form a circuit that performs a desired function, such as a microprocessor for processing data or a memory device for storing data. To interconnect the millions of components contained in many integrated circuits, connections or “contacts” to each device are formed using conductive materials such as metal and polysilicon, as will be appreciated by those skilled in the art.
FIG. 1
is a diagram illustrating several silicon contacts
100
,
102
,
104
that have been selectively formed on a silicon substrate
106
using a conventional selective deposition method, such as selective epitaxial growth (“SEG”). In an ideal SEG process, the contacts
100
-
104
are selectively formed only on exposed regions
108
-
112
of the substrate
106
, respectively, and are not formed on other exposed regions of the substrate such as the surfaces of isolation oxide regions
114
and
116
. Each of the regions
108
-
112
typically includes a device (not shown), such as a metal oxide semiconductor (“MOS”) transistor or diode, and the corresponding contact
100
-
104
is formed on the region to provide contact to the device. Although the contacts
100
-
104
and substrate
106
are described as being silicon in the example of
FIG. 1
, the general concepts being discussed apply to other materials as well, as will be understood by those skilled in the art.
FIG. 1
illustrates a potential problem that arises when selectively forming the silicon contacts
100
-
104
due to the horizontal or lateral growth
118
of the contacts in the direction indicated by the arrows. In an ideal SEG process, the contacts
100
-
102
are formed only through vertical growth
120
in the direction indicated by the arrow, and in this way the contacts form only on the exposed regions
108
-
112
of the substrate
106
and not on the isolation oxide regions
114
,
116
. Due to the lateral growth
118
, however, the contacts
100
-
104
grow towards each other and over the isolation oxide regions
114
,
116
. As illustrated for the contact
102
, the lateral growth
118
results from silicon being deposited on an upper surface
122
while also being deposited on sidewalls
124
,
126
of the contact during formation, as will be understood by those skilled in the art. The contact
102
grows in both the vertical and lateral directions at the same rate.
The lateral growth
118
may result in adjacent contacts undesirably touching each other, as indicated by the dotted lines
122
between the contacts
100
and
102
. When the contacts
100
and
102
touch, an unwanted short circuit occurs and the devices being fabricated may not operate properly. As the size of devices being formed in integrated circuits continues to decrease, the distance between adjacent contacts
100
,
102
and
102
,
104
also decreases, making lateral growth
118
a concern since less lateral growth is required before adjacent contacts short circuit. While the amount of lateral growth of the contacts
100
-
104
can be reduced by forming the contacts for a shorter period of time, this is not a viable in most applications because the contacts must be formed to a desired height H, as indicated for the contact
100
. As will be appreciated by those skilled in the art, the contacts
100
-
104
must reach the desired height H, for example, in order to ensure subsequent layers (not shown) can reliably connect to the contacts to provide electrical connection to the underlying devices. For example, in a MOS transistor contacts it is desirable that contacts being formed to source and drain regions of the transistor are at least as high as a gate stack formed over a channel region of the transistor to ensure subsequent layers form proper connection to the contacts.
There is a need for a method of selectively forming silicon contacts of desired heights in integrated circuits having reduced device sizes.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, a method of selectively forming contact regions on a substrate having a plurality of exposed regions includes selectively forming a contact region on each of the exposed regions of the substrate. During formation, each contact region has a first growth rate in a first direction and a second growth rate in a second direction. While each contact region is being selectively formed on the respective exposed region, the contact region is heated to increase the first growth rate of the contact region in the first direction relative to the second growth rate of the contact region in the second direction. The first growth rate may be a vertical growth rate and the second growth rate may be a lateral growth rate. The contact may be heated by applying electromagnetic radiation to an upper surface of the substrate and not applying the radiation to the vertical portions of the contact region to thereby increase the vertical growth rate relative to the lateral growth rate. The electromagnetic radiation may be collimated light such as that generated by a scanning laser beam, and the substrate and formed contact regions may be silicon or other suitable materials. This method may be used during the fabrication of MOS transistors in memory devices and other integrated circuits.
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J. W. Siekkinen, W. A. Klaasen, G. W. Neudeck, “Selective Epitaxial Growth Silicon Bipolar Transistors for Material Characterization,” 1988 Bipolar Circuits and Technology Conference, Minneapolis, Minn., Oct. , pp. 1640-1644, 1988.*
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P. Rai-Choudhury, D.K. Schroder, “Selective Growth of Epitaxial Silicon and Gallium Arsenide,” Jan. 1971 Westinghouse Research Laboratories, Pittsburgh, Pennsylvania, pp. 107-110.*
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Boman, M. et al., “Helical Microstructures Grown by Laser Assisted Chemical Vapour Deposition”, Micro Electro Mechanical Systems, Feb. 4-7, 1992, pp. 162-167.
Wallenberger, F.T., “Rapid Prototyping Directly from the Vapor Phase (Laser-assisted Chemical capor Deposition)”, American Association for the advancement of Science, Mar. 3, 1995, pp. 1-5.
Westberg, H. et al., “Truly Three Dimensional Structures Microfabricated by Laser Chemical Processing”, IEEE, 1991, pp. 516-519.
Mercaldi Garry Anthony
Nuttall Michael
Dorsey & Whitney LLP
Ho Hoai
Micro)n Technology, Inc.
Vu David
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