Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-09-27
2002-02-12
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S597000
Reexamination Certificate
active
06346476
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to methods for forming inter-metal dielectric (IMD) layers within microelectronic fabrications. More particularly, the present invention relates to methods for forming with enhanced line-to-line capacitance uniformity inter-metal dielectric (IMD) layers within microelectronics fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels have increased and microelectronic device and patterned microelectronic conductor layer dimensions have decreased, it has become increasingly more important within the art of microelectronic fabrication to form interposed between the patterns of patterned microelectronic conductor layers within microelectronic fabrications microelectronic dielectric layers formed of low dielectric constant dielectric materials. Low dielectric constant dielectric materials are desirable for forming microelectronic dielectric layers formed interposed between the patterns of patterned microelectronic conductor layers within microelectronic fabrications since such low dielectric constant dielectric materials provide, among other features, microelectronic fabrications with enhanced microelectronic fabrication speed and reduced patterned microelectronic conductor layer cross-talk.
For the purposes of the present disclosure, low dielectric constant dielectric materials are intended as dielectric materials having a dielectric constant (relative to vacuum) of preferably less than about 3.8, and more preferably from about 2.0 to about 3.8. For comparison purposes, conventional dielectric materials which are typically employed within microelectronic fabrications, such conventional dielectric materials including but not limited to silicon oxide dielectric materials, silicon nitride dielectric materials and silicon oxynitride dielectric materials, typically have dielectric constants in the range of from about 4.0 to about 8.0.
Of the low dielectric constant dielectric materials which may be employed for forming low dielectric constant dielectric layers within microelectronic fabrications, fluorosilicate glass (FSG) low dielectric constant dielectric materials have recently received considerable interest and attention. Within the context of the present application, fluorosilicate glass (FSG) low dielectric constant dielectric materials are intended as non-stoichiometric silicon oxide dielectric materials which have incorporated therein a fluorine dopant at a concentration of from about 2 to about 10 or atom percent. Such fluorosilicate glass (FSG) low dielectric constant dielectric materials typically have a dielectric constant of from about 3.3 to about 3.8. Fluorosilicate glass (FSG) low dielectric constant dielectric materials are generally of considerable interest insofar as they may under certain circumstances be formed by employing comparatively minor modifications of methods which are conventionally employed for forming silicon oxide dielectric materials within microelectronic fabrications.
While low dielectric constant dielectric layers formed of fluorosilicate glass (FSG) low dielectric constant dielectric materials are thus desirable within the art of microelectronic fabrication, low dielectric constant dielectric layers formed of fluorosilicate glass (FSG) low dielectric constant dielectric materials are nonetheless not entirely without problems within the art of microelectronic fabrication. In particular, it is known in the art of microelectronic fabrication that low dielectric constant dielectric layers formed of fluorosilicate glass (FSG) low dielectric constant dielectric materials are often chemically unstable incident to the incorporation therein of loosely bound mobile fluorine atoms. Similarly, it has also been observed that it is often difficult to form low dielectric constant dielectric layers from fluorosilicate glass (FSG) low dielectric constant dielectric materials with optimally uniform electrical properties, such as but not limited to line-to-line capacitance.
It is thus towards the goal of forming within a microelectronics fabrication a low dielectric constant dielectric layer formed of a fluorosilicate glass (FSG) low dielectric constant dielectric material, with uniform electrical properties, that the present invention is more particularly directed. In a more general sense the present invention is also directed towards the goal of forming within a microelectronic fabrication a silicon containing dielectric layer, which need not necessarily be formed of a fluorosilicate glass (FSG) low dielectric constant dielectric material, with uniform electrical properties.
Various methods and apparatus have been disclosed within the art of microelectronic fabrication for forming dielectric layers, such as low dielectric constant dielectric layers formed of fluorosilicate glass (FSG) low dielectric constant dielectric materials, with desirable properties within microelectronic fabrications.
For example, Jain, in U.S. Pat. No. 5,621,241, discloses a semiconductor integrated circuit microelectronics fabrication, and a method for forming the semiconductor integrated circuit microelectronic fabrication, where a dielectric layer employed for separating a series of patterns within a patterned conductor layer within the semiconductor integrated circuit microelectronic fabrication is formed with improved fabrication throughput, improved gap-fill planarity and improved within-wafer uniformity. To realize the foregoing objects, the method employs a gap-fill dielectric layer formed upon the patterned conductor layer while employing a high density plasma chemical vapor deposition (HDP-CVD) method, where the gap-fill dielectric layer has formed thereupon a sacrificial dielectric polish layer which has an enhanced chemical mechanical polish (CMP) rate with respect to the gap-fill dielectric layer.
In addition, Ravi et al., in U.S. Pat. No. 5,661,093, discloses a method and apparatus for forming within a microelectronics fabrication a halogen doped silicon oxide dielectric layer with enhanced resistance to moisture absorption and outgassing. To realize the foregoing objects, the method employs when forming the halogen doped silicon oxide layer a multiplicity of carbon rich sealing layers or undoped silicon oxide sealing layers interposed between a series of halogen doped silicon oxide dielectric sub-layers which comprise the halogen doped silicon oxide dielectric layer.
Further, Lou, in U.S. Pat. No. 5,759,906, discloses a method for forming within a microelectronic fabrication a planarized inter-metal dielectric (IMD) layer comprising a low dielectric constant dielectric material comprising a spin-on-glass (SOG) dielectric material or a spin-on-polymer (SOP) dielectric material: (1) without directly planarizing the low dielectric constant dielectric material, and (2) while not exposing within a via formed through the planarized inter-metal dielectric (IMD) layer the low dielectric constant dielectric material comprising the spin-on-glass (SOG) dielectric material or the spin-on-polymer (SOP) dielectric material. To realize the foregoing objects, there is first employed when forming the planarized inter-metal dielectric (IMD) layer a dielectric capping layer (which may be formed of a fluorosilicate glass (FSG) low dielectric constant dielectric material) where the dielectric capping layer is partially chemical mechanical polish (CMP) planarized without planarizing the low dielectric constant dielectric material comprising the spin-on-glass (SOG) dielectric material or the spin-on-polymer (SOP) dielectric material. There is then also formed an annular dielectric spacer layer (which also may be formed of a fluorosilicate glass (FSG) low dielectric constant dielectric material) into a via formed through the partially chemical mechanical polish (CMP) planar
Chang Weng
Jang Syun-Ming
Ackerman Stephen B.
Nelms David
Saile George O.
Stanton Stephen G.
Taiwan Semiconductor Manufacturing Company
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