Abrading – Abrading process – Glass or stone abrading
Reexamination Certificate
1999-08-06
2001-01-30
Young, Lee (Department: 3729)
Abrading
Abrading process
Glass or stone abrading
C451S028000, C451S036000, C451S288000
Reexamination Certificate
active
06179691
ABSTRACT:
BACKGROUNG OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of end point detection for the copper Chemical Mechanical Polishing process.
(2) Description of the Prior Art
In forming semiconductor devices a large number of complex processing steps are required to form particular device features, these processing steps typically use and depend on a flat surface in order to perform their operation. The creation of semiconductor devices further results in creating these devices in a number of layers of material which further complicates the required processing steps since planarity must also be maintained from layer to layer within the device structure. Good surface planarity is critically important to lithography processes since these processes depend on maintaining depth of focus. Two common techniques used to achieve planarity on a semiconductor surface are a Spin-On-Glass (SOG) etchback process and a Chemical Mechanical Polishing (CMP) process. Although both processes improve planarity on the surface of a semiconductor wafer, CMP has been shown to have a higher level of success in improving global planarity.
Because dimensions if Integrated Circuit (IC) devices within advanced IC's continue to decrease, the dimensions of conductors and interconnection elements, which connect and interconnect those integrated circuit devices, also continue to decrease. Dimensions of conductor and interconnection elements which directly contact IC devices have typically decreased the greatest, thus becoming the smallest in dimension of conductor and interconnecting elements within advanced IC's. These narrow conductor and interconnection elements typically comprise the first conductor or interconnection level, which contacts an integrated circuit device. First conductor levels have traditionally been formed from aluminum metal or aluminum metal alloys. First interconnection levels (i.e. first conductive contact studs) are typically formed using tungsten. Conducting lines in the era of micron and sub-micron device features must have a high level of conductivity while simultaneously showing limited susceptibility to degradative phenomenon such as electromigration, a requirement that grows in importance as wire widths decrease. Electromigration may, under extremely high current densities, result in an electrical open and is most common in aluminum metal and aluminum metal alloy conductor and interconnect elements and has not typically been observed in interconnects made of tungsten. Although copper metal and copper metal alloys possess the high electrical conductivity and low electromigration susceptibility desired for conductor elements and interconnection elements within advanced IC's, methods through which copper and copper metal alloys may be formed into conductor and interconnection elements within advanced IC's are neither entirely well developed nor entirely well understood.
Copper is seen as an attractive replacement for aluminum because of its low cost and ease of processing. Copper does however present a particular problem related to copper's high susceptibility to oxidation. Conventional photoresist processing cannot be used when the copper is to be patterned into various wire shapes because the photoresist needs to be removed at the end of the process by heating it in a highly oxidized environment, such as an oxygen plasma, thereby converting it to an easily removed ash.
Chemical Mechanical Polishing (CMP) is a method of polishing materials, such as semiconductor substrates, to a high degree of planarity and uniformity. A typical CMP process involves the use of a polishing pad made from a synthetic fabric and a polishing slurry, which includes pH-balanced chemicals, such as sodium hydroxide, and silicon dioxide particles. The process is used to planarize semiconductor slices prior to the fabrication of semiconductor circuitry thereon, and is also used to remove high elevation features created during the fabrication of the microelectronic circuitry on the substrate. One typical chemical mechanical polishing process uses a large polishing pad that is located on a rotating platen against which a substrate is positioned for polishing, and a positioning member which positions and biases the substrate on the rotating polishing pad. Chemical slurry, which may also include abrasive materials, is maintained on the polishing pad to modify the polishing characteristics of the polishing pad in order to enhance the polishing of the substrate.
The motion of the wafer relative to the polishing pad creates abrasive action. The pH of the polishing slurry controls the chemical reactions, e.g. the oxidation of the chemicals which comprise an insulating layer of the wafer, while the size of the silicon dioxide particles controls the physical abrasion of the surface of the wafer. The polishing of the wafer is accomplished when the silicon dioxide particles abrade away the oxidized chemicals. An importance parameter during the polishing operation is the polishing efficiency, which is the amount of material that is removed from the surface of the substrate by the CMP process as a function of time. This efficiency is dependent on the density of the pattern or the concentration of the raised areas on the surface that is being polished.
During the CMP process, the allocated polishing time and the downforce exerted on a wafer that is being polished are typically fixed and independent of the topography of the surface that is being polished. The removal rate of material from a wafer has been shown to be directly proportional to the downward force exerted on the surface that is being polished and inversely proportional to the surface area that comes into contact with the polishing pad. The removal rate of material therefore increases as the polished surface decreases, and visa versa. Since different integrated circuits have different surface topographies, the material removed during a CMP process may vary from substrate to substrate and between various layers within a device structure.
The use of metals to interconnect the various elements of a semiconductor device as either intra-level or inter-level connectors has also required considerable attention. Electrical conductors are made of electrically conductive material, a suitable material includes Al, Al alloy, Cu, Cu alloy, Ag, Ag alloy, Si, Ti, Ta, W (tungsten), W alloy, Mo, polysilicon, or a combination thereof and oxides of these metals. Aluminum is typically used as a conductive material, however the use of tungsten and copper for conducting lines or inter-level vias has gained considerable attention in recent years.
Aluminum is typically used in upper-layer wiring. Since however copper has lower resistivity, the use of copper for conductive interfaces is being investigated. Copper is however very difficult to process by Reactive Ion Etch (RIE), the CMP method has therefore been studied for using copper as a wiring material. To polish copper at a high rate of polishing efficiency without causing surface scratching, the copper etch rate must be raised by increasing the amount of the component in the polishing slurry that is responsible for copper etching. If this component is increased to a high level, the etching will become an isotropic etch. Under these conditions, buried copper is etched away causing dishing in the wiring. It is therefore difficult to form highly reliable LSI copper wiring.
The use of copper has become increasingly more important for the creation of multilevel interconnections in semiconductor circuits, however copper lines frequently show damage after CMP and clean. This damage of copper lines causes planarization problems of subsequent layers that are deposited over the copper lines because these layers may now be deposited on a surface of poor planarity. Particularly susceptible to damage are isolated copper lines or copper lines that are adjacent to open fields. While the root causes for these damages are at thi
Chen Chien-Chen
Huang Hsin-Chieh
Lee Fu-Sheng
Lee Jiun-Chung
Ackerman Stephen B.
Saile George O.
Taiwan Semiconductor Manufacturing Company
Trinh Minh
Young Lee
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