Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Utility Patent
1998-08-18
2001-01-02
De Cady, Albert (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S763000
Utility Patent
active
06170077
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for encoding a digital communication channel, and in particular, to an improved method for encoding a digital communication channel which is capable of enhancing the performance of a digital communication based on a convolutional encoding and interleaving technique.
2. Description of the Conventional Art
As shown in
FIG. 1
; the conventional method for encoding a digital communication channel includes a frame input data register
110
for receiving a frame data for implementing a channel encoding operation, a write address control circuit
120
for storing an input data into an ERAM (encoder RAM), a read address control circuit
130
for reading the data stored in the ERAM, an ERAM
140
for storing the frame data input, a parallel-serial converter
150
for reading a data from the ERAM and converting the data, a convolutional encoder
160
for receiving a serial input data and generating a code symbol, a write address control circuit
180
for controlling the code symbol generated for implementing an interleaving operation, an interleaver RAM (hereinafter called IRAM)
170
for storing a code symbol , and a read address control circuit
190
for reading the data from a boundary of the frame in a form of row at a predetermined time and implementing a channel encoding operation.
The data of one frame inputted through the frame input data register
110
are sequentially inputted into the ERAM
140
in accordance with the micro controller and the write address control circuit
120
for implementing a channel encoding operation.
The data stored in the ERAM are sequentially read at a predetermined time earlier than the time computed at the boundary of the next frame and are inputted into the convolutional encoder
160
through the parallel-serial converter
150
for thereby generating a code symbol, and then the code symbol generated for implementing the interleaving operation is stored into the IRAM
170
in accordance with a control of the write address control circuit
180
, and the thusly stored data are read in a form of row at a predetermined time in accordance with a control of the read address control circuit
190
from the boundary of the frame for thereby implementing a channel encoding operation.
FIG. 2
illustrates a signal timing method for a conventional channel encoder which includes a step S
1
in which a data request interrupt signal is received and a controller writes an input data into a frame input data register. In a step S
2
, the input data stored in the frame input data register are sequentially inputted into the ERAM
140
. Thereafter, when the data of one frame are all inputted, the convolutional encoding operation becomes a ready state for an ERAM read time.
In the above described construction, the operation that the input data of one frame are buffered into the ERAM and then are read for thereby implementing a convolutional encoding operation is simply performed. In order to perform the interleaving operation, the data should be written into the IRAM within one frame time, and one frame should equally be divided and then the data stored in the IRAM is read at a predetermined time. In the conventional art, it is difficult to control the timing.
For implementing the above-described timing control, all of the data stored in the IRAM are written at a time between the final IRAM read time of the previous frame and the initial IRAM read time of the current frame, and the data used at the time when the data stored in the IRAM are read in a form of row are written into the IRAM. Namely, the above described IRAM write and read operations may be used. There is a limit in that the micro controller stores a frame input data into the register by avoiding the time when the data are read from the ERAM and then encoded. In addition, additional control operation is required for adjusting the position of a data request interrupt.
In Steps S
3
and (
FIG. 2
) S
4
, the data stored in the ERAM are sequentially read at the boundary of the frame for a predetermined computed time, and the convolutional encoding operation is performed with respect to the first frame.
In Step S
5
, the code symbol from the convolutional encoder is sequentially stored into the IRAM from the first address.
The data read from the IRAM at the time which is obtained by equally dividing one frame at the boundary of the frame in Step S
6
for thereby implementing a channel encoding operation of the initial frame, and then the input data of the second frame are received in Step S
7
, and the channel encoding operation of the second frame is performed in the same manner as the first frame.
Namely, in order to implement the channel encoder which used a convolutional encoding operation and an interleaving operation, the IRAM which is capable of implementing a large size by the inverse proportion of encoding rate R compared to the ERAM is required. Namely, a circuit and timing control circuit capable of generating an address for performing a write and read operation of the IRAM is required within one frame time.
In addition, it is impossible to write the frame input data into the frame input data register while the convolutional encoding operation is performed and the data stored in the ERAM are read by the micro controller. In addition, in order to overcome the above problem, the position of the data request interrupt should be adjusted for thereby additionally requiring a control operation.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method for encoding a digital communication channel which overcomes the aforementioned problems encountered in the conventional art.
It is another object of the present invention to provide a method for encoding a digital communication channel which is capable of implementing a convolutional encoding and interleaving operation at a time by alternately using two RAMS for a frame input data buffering operation having a small size by the ratio of encoder rate R compared to the interleaver RAM without using an interleaver RAM having a large memory space and a high test cost compared to the conventional art which is directed to using a RAM for storing a frame data inputted for a channel encoding operation and another RAM for an interleaving operation of a code symbol which is an output of the convolutional encoder, thereby decreasing the number of hardware for a channel encoder and implementing a simple and a predetermined margin of a protocol when changing a micro controller and a frame input data packet.
In order to achieve the above objects, there is provided a method for encoding a digital communication channel which includes the steps of first storing a frame data, which is inputted for a channel encoding operation, into an encoder RAM (ERAM0); second addressing the ERAM and storing the data into a register via a multiplexer in accordance with a control of a frame selection signal; third addressing the ERAM for reading an input data before the previous input data and storing the read data into the register; fourth selecting an input data among two register output data, inputting the selected input data into the convolutional encoder and generating a code symbol; and fifth selecting one among the code symbols and obtaining an output of the channel encoder that completed the convolutional encoding and interleaving operations.
Additional advantages, objects and other features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.
REFERENCES:
patent: 4298954 (1981-11-01), Bigelow et al.
patent: 5042033 (1991-08-01), Costa
patent: 5065346 (1991-11-01), Kawai et al.
patent: 5103459 (1992-04-01), Gilhousen et al.
patent: 5163132 (1992-11-
Kim Kyung Soo
Lee Seong Bong
Lim In Gi
Yeon Kwang Il
Cady Albert De
Cohen & Pontani, Lieberman & Pavane
Electronics and Telecommunications Research Institute
Ton David
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