Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Patent
1999-01-07
2000-10-31
Hiteshen, Felisa
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
438694, 438697, 438699, 438706, 438723, H01L 21302
Patent
active
061402400
ABSTRACT:
A method of removing microscratches in planarized dielectric surfaces covering conductor layers in submicron integrated circuit structures includes a semiconductor substrate having at least one dielectric layer formed thereon followed by a chemical mechanical polishing process for planarization. The removal of microscratches includes depositing a PE-CVD polymer layer to fill the microscratches, caused by CMP planarization, and to cover the planarized dielectric surface with a thin layer of the polymer. Deposition is followed by introducing an etching gas into the CVD chamber for an etch back of the just deposited polymer to well below the depth of the microscratches wherein the deposited polymer has the same etch rate as the dielectric layer formed thereunder.
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Chen Bi-Ling
Jeng Erik S.
Lin Bih-Tiao
Yang Fu-Liang
Yen Tzu-Shih
Ackerman Stephen B.
Hiteshen Felisa
Saile George O.
Tran Binh X.
Vanguard International Semiconductor Corporation
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