Method for dual stress liner

Details Method for dual stress liner Method for dual stress liner

2011-05-17

2011-05-17

Vu, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S204000, C257SE21635

Reexamination Certificate

active

07943454

ABSTRACT:
A semiconductor device structure is provided which includes a first field effect transistor (“FET”) having a first channel region, a first source region, a first drain region and a first gate conductor overlying the first channel region. A second FET is included which has a second channel region, a second source region, a second drain region and a second gate conductor overlying the second channel region. The first and second gate conductors can be portions of a single elongated conductive member extending over both the first and second channel regions. A first stressed film may overlie the first FET and the first stressed film may apply a stress having a first value to the first channel region. A second stressed film may overlie the second FET and the second stressed film may apply a stress having a second value to the second channel region. The second value is substantially different from the first value. The first and second stressed films can abut each other at a common boundary and present a substantially co-planar major surface at the common boundary.

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