Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-11-16
2001-03-06
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06197632
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to integrated circuit product and processes. More particularly, the invention relates to high performance Dynamic Random Access Memory (DRAM) chips and processes for making such chips.
Present processing of DRAM structures typically utilizes a thick sidewall oxidation after gate conductor etch. The sidewall oxidation improves array retention time by a stress relief anneal of the wafer, and also by developing a significant bird's beak at the transfer gate device edges. The extended oxidation reduces electric fields and potentially helps with ameliorating defect densities. Currently, extension and halo implants are then performed after the sidewall oxidation step, which necessitates increased energy implants and causes deeper junctions. The deeper junctions may not be desirable for all or some of the logic support devices that are often disposed adjacent to the DRAM array. Splitting sidewall oxidation into two steps does not provide an adequate solution since the dopants in the support logic devices are exposed to thermal processing of the DRAM array at elevated temperature, which causes diffusion of the dopants that still results in deep Junctions. Therefore, a process is desired wherein a DRAM array may be provided with a thick sidewall oxidation while providing for shallow junctions in some or all of the support logic devices.
SUMMARY OF THE INVENTION
According to an aspect of the invention, an IC fabrication structure is provided, comprising: a silicon wafer; a DRAM array fabrication disposed on the silicon wafer having a first multitude of gate sidewall oxides; and a logic support device fabrication disposed on the wafer adjacent the DRAM array fabrication and having a second multitude of gate sidewall oxides, the first multitude of gate sidewall oxides being substantially thicker than the second multitude of gate sidewall oxides.
According to a further aspect of the invention, an IC fabrication method is provided, comprising the steps of: forming a DRAM array fabrication on a silicon wafer having a first multitude of gate sidewall oxides; and, forming a logic support device fabrication on a silicon wafer having a second multitude of gate sidewall oxides, the first multitude of gate sidewall oxides being substantially thicker than the second multitude of gate sidewall oxides.
According to a still further aspect of the invention, an IC fabrication method is provided, comprising the steps of: forming a DRAM array fabrication on a silicon wafer having a first multitude of gate sidewall oxides and a logic support device fabrication having a second multitude of gate sidewall oxides adjacent to the DRAM array fabrication; subsequently doping the DRAM array fabrication; subsequently increasing thickness of the first multitude of gate sidewall oxides so that they are substantially thicker than the second multitude of gate sidewall oxides; and, subsequently doping the logic support device fabrication.
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patent: 5863820 (1999-01-01), Huang
Bronner Gary B.
Divakaruni Rama
Halle Scott
Martin Dale W.
Rengarajan Rajesh
Brinks Hofer Gilson & Lione
Chaudhari Chandra
International Business Machines - Corporation
Thompson Craig
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