Radiation imagery chemistry: process – composition – or product th – Imaging affecting physical property of radiation sensitive... – Making electrical device
Reexamination Certificate
2002-04-25
2004-07-20
Duda, Kathleen (Department: 1756)
Radiation imagery chemistry: process, composition, or product th
Imaging affecting physical property of radiation sensitive...
Making electrical device
C430S317000, C430S329000
Reexamination Certificate
active
06764810
ABSTRACT:
FIELD OF THE INVENTION
This invention generally relates to photolithographic patterning of semiconductor features and more particularly to an improved method for manufacturing features such as dual damascene structures while eliminating problems caused by undeveloped photoresist.
BACKGROUND OF THE INVENTION
Since the introduction of semiconductor devices, the size of semiconductor devices has been continuously shrinking, resulting in smaller semiconductor chip size and increased device density. One of the limiting factors in the continuing evolution toward smaller device size and higher density has been the stringent requirements placed on photolithographic processes as line width and step heights have decreased for device features. As one way to overcome such limitations, various methods have been implemented to increase the resolution performance of photoresists and to eliminate interfering effects occurring in the semiconductor wafer manufacturing process.
In the fabrication of semiconductor devices multiple layers may be required for providing a multi-layered interconnect structure. During the manufacture of integrated circuits it is common to place material photoresist on top of a semiconductor wafer in desired patterns and to etch away or otherwise remove surrounding material not covered by the resist pattern in order to produce metal interconnect lines or other desired features. During the formation of semiconductor devices it is often required that the conductive layers be interconnected through holes in an insulating layer. Such holes are commonly referred to as vias, i.e., when the hole extends through an insulating layer between two conductive areas. Metal interconnecting lines (trench lines) are typically formed over the vias to electrically interconnect the various semiconductor devices within and between multiple layers. The damascene process is a well known semiconductor fabrication method for forming electrical interconnects between layers by forming vias and trench lines.
For example, in the dual damascene process, a via is etched in an insulating layer also known as an inter-metal or inter-level dielectric (IMD/ILD) layer. The insulating layer is typically formed over a metal or conductive layer. After a series of photolithographic steps defining via openings and trench openings, the via openings and the trench openings are filled with a metal (e.g., Al, Cu) to form vias and trench lines, respectively. The excess metal above the trench level is then removed by well known chemical-mechanical polishing (CMP) processes.
After the via holes are etched, but before the holes are filled with a conductive material, for example, copper, the photoresist mask which remains on top of the desired features may be removed by a dry etching method known as a reactive ion etch (RIE) or ashing process using a plasma formed of O
2
or a combination of CF
4
and O
2
to react with the photoresist material.
As feature sizes in etching process have become increasingly smaller, photolithographic processes have been required to use photoresist activating light (radiation) of smaller wavelength. Typically a deep ultraviolet (DUV) activating light source with wavelength less than about 250, but more typically, from about 193 nm to about 230 nm is used. Exemplary DUV photoresists, for example, include PMMA and polybutene sulfone.
One problem affecting DUV photoresist processes has been the interference of residual nitrogen-containing species with the DUV photoresist. Residual nitrogen-containing contamination is one of the greater concerns in the use or application of metal nitride films such as silicon nitride or silicon oxynitride as hard mask layer or silicon oxynitride as a DARC. For example, nitrogen radicals created due to the presence of nitrogen containing species, such as amines, interfere with chemically amplified resists by neutralizing the acid catalyst, thereby rendering that portion of the photoresist insoluble in the developer. As a result, residual photoresist may remain on patterned feature edges, walls, or floors of features, affecting subsequent etching or metal filling processes thereby degrading electrical property functionality by causing, for example, electrical open circuits or increased resistivity.
Another aspect of advances in semiconductor device processing technology that exacerbates the problem is the increasing use of low-k (low dielectric constant) insulating materials that make up the bulk of a multilayer device. Low-k materials are increasingly used in, for example insulating (IMD) layers to reduce signal delays caused by parasitic capacitance effects. Many of the low-k materials are designed with a high degree of porosity including interconnecting porosity to allow the achievement of lower dielectric constants. The problem of absorption chemical species that interfere with subsequent processes is exacerbated by the tendency of porous low-k materials to readily absorb and transport such chemical species.
There is therefore a need in the semiconductor processing art to develop a method whereby reliable photolithography processes may be carried out without the-detrimental effects of photoresist poisoning.
It is therefore an object of the invention to provide a method whereby reliable photolithography processes may be carried out without the detrimental effects of photoresist poisoning while overcoming other shortcomings and deficiencies in the prior art.
SUMMARY OF THE INVENTION
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method for improving a photolithographic patterning process in a dual damascene process.
In a first embodiment, the method includes providing at least one via opening in a substrate including a low dielectric constant material; blanket depositing a photo-sensitive resinous layer to fill the at least one via opening; partially removing the photo-sensitive resinous layer to form an at least partially filled via plug; photo-curing the via plug such that an activating light source causes a polymer cross-linking chemical reaction; and, forming a trench line opening disposed substantially over the at least one via opening using a trench line photoresist to pattern the trench line opening.
REFERENCES:
patent: 6211068 (2001-04-01), Huang
patent: 2002/0045107 (2002-04-01), Holscher
Chen Tsung-Chuan
Fan Chun-Liang
Ma Ching-Tien
Duda Kathleen
Taiwan Semiconductor Manufacturing Co. Ltd
Tung & Associates
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