Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-11-28
2002-08-13
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S514000, C438S914000, C438S942000
Reexamination Certificate
active
06432783
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor device and to a method for manufacturing a highly integrated semiconductor device.
2. Background of the Related Art
The increasing integration of semiconductor devices has resulted in a reduction in design parameters. Therefore, current trends in manufacturing design reduce cell size to include reductions of gate electrode width and a channel length.
However, reduction of the cell size for high integration has limitations. Also, problems in operation and reliability of the devices remain even though the cell size is reduced. Particularly, the width of the gate electrode is very narrow in subminiature semiconductor devices, and this results in some problems.
One problem is gate induced drain leakage (GIDL). GIDL occurs in a trench-isolation structure and particularly in the three-dimensional (3-D) intersection of the gate-to-drain and the trench corner.
Typically, an electric field generated at a two-dimensional (2-D) region of the gate-to-drain overlap. In the trench isolation structure, the electric field at the 3-D intersection is significantly higher than the 2-D gate-to-drain overlap region by GIDL at the trench corner.
A related art method for manufacturing a semiconductor device will now be described with reference to the appended drawings.
In the related art method, a polygate is doped when forming MOS devices such as NMOS, PMOS and CMOS.
FIGS. 1
a
and
1
b
show a method for doping the polygate in forming the CMOS device.
FIG. 1
a
shows a region A at which a PMOS device will be formed and a region B at which a NMOS device will be formed.
A first active region
11
and a second active region
11
a
are isolated from each other by a device isolation region formed by a trench isolation process. The first active region
11
is an active region of the PMOS device while the second active region
11
a
is an active region of the NMOS device.
Subsequently, a polysilicon layer on which impurities are not doped is formed on the whole surface of the active regions and then patterned to form a polygate
12
across the first and second active regions
11
and
11
a.
Impurities are doped on the polygate
12
. The doping is possible by one of two steps. One step is to separately dope the impurities on the polygate
12
only. The other step is to dope the impurities on the polygate
12
simultaneous with injecting the impurities into source/drain regions.
Typically, the concentration of the impurities for the polygate is higher than that for the source/drain regions. Accordingly, when the polygate and the source/drain regions are doped with the impurities by separate doping steps, the concentration of the Impurities for the source/drain regions is lower than that for the polygate.
However, when the polygate and the source/drain are simultaneously doped with the impurities, the concentration of the impurities for the source/drain region should be higher than that for the polygate. That is, the general concentration of the impurities for the source/drain regions is insufficient to dope the polygate. Therefore, the concentration of the impurities for the source/drain regions should be made higher than the general concentration so as to satisfy the doping concentration of the polygate.
In the related art method, the polygate is doped with the impurities by injecting the impurities into the source/drain regions. As illustrated in
FIG. 1
a
, a first mask
13
is formed so that the region A is exposed. Afterwards, the polygate
12
is formed. That is, the first mask
13
exposes only the region A. Then, impurity ions of P conductive type are injected into the whole surface to dope the polygate
12
and the first active region
11
.
Accordingly, the impurities are doped on the exposed polygate
12
and also doped on the first active region
11
which is at both sides of the polygate
12
, so that source/drain impurity regions
14
and
15
of PMOS are formed.
The injected impurities are B ions or BF
2
ions.
As illustrated in
FIG. 1
b
, the first mask
13
is removed and a second mask
16
is formed so as to expose the region B. Impurity ions of N conductive type are injected into the whole surface so that exposed portions of the polygate
12
and the second active region
11
a
are doped with the impurity ions.
As a result, the N conductive type impurities are doped on the polygate
12
and the second active region
11
a
, so that source and drain impurity regions
17
and
18
of NMOS are formed.
The injected impurities are As ions or P ions.
The related art is further explained by
FIG. 2
a
, which is a sectional view taken along line
2
a
—
2
a
of
FIG. 1
a
. The polygate forms by doping through an open region of a mask. As a result of doping into the whole surface, an electric field converges at the corner of the active region A by the gate electrode.
FIG. 2
b
shows a sectional view taken along line
2
b
—
2
b
of
FIG. 1
a
. When an electric field is converges at the corner of the active region by the gate electrode, a channel is formed between the source and the drain by charges at the corner of the active region.
The aforementioned related art method for manufacturing a semiconductor device has several problems.
Reducing the device size results in that the electric field by the gate is stronger at the corner of the active region than other regions, so that the threshold voltage of the active region is lowered. Accordingly, a current generates during the off state in which the voltage between the drain and the source is low. This increases power consumption. Particularly, this problem becomes more serious as the channel becomes narrower.
SUMMARY OF THE INVENTION
Accordingly, the invention is directed, in part, to a method for manufacturing a semiconductor device that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
The invention, in part, provides a semiconductor device in which no current generates during the off state by reducing the electric field at the corner of an active region.
The invention, in part, provides a method for manufacturing a semiconductor device in which no current generates during the off state by reducing the electric field at the corner of an active region.
The invention, in part, provides a method for manufacturing a semiconductor device that includes the steps of patterning a gate material layer on a portion on an active region of a semiconductor substrate; forming a mask having an open region over at least a portion of the active region but not substantially over a field region of the semiconductor substrate; and forming a gate electrode, source regions and drain regions by doping impurity ions of a conductive type opposite to that of the exposed gate material layer and the active region.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 4256829 (1981-03-01), Daniel
patent: 5681769 (1997-10-01), Lien
patent: 6211555 (2001-04-01), Randazzo et al.
patent: 6297111 (2001-10-01), Krivokapic
S. Geissler et al., “A New Three-Dimensional MOSFET Gate-Induced Drain Leakage Effect in Narrow Deep Submicron Devices”, IEDM, 839-842, 1991.
Elms Richard
Hyundai Electronics Industries Co,. Ltd.
Pyonin Adam
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