Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1997-11-03
2001-03-13
Moise, Emmanuel L. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S025000, C714S047300, C714S732000, C324S076110
Reexamination Certificate
active
06202181
ABSTRACT:
REFERENCE TO A MICROFICHE APPENDIX
Not Applicable
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All of the material in this patent document is subject to copyright protection under the copyright laws of the United States and of other countries. The owner of the copyright has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the United States Patent and Trademark Office file or records, but otherwise reserves all copyright rights whatsoever.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention pertains generally to failure analysis methods applied to electronic circuitry, and more particularly to a method for diagnosing bridging faults in integrated circuits.
2. Description of the Background Art
Ensuring the high quality of integrated circuits (IC) is important for many reasons, including high production yield, confidence in fault-free circuit operation, and the reliability of delivered parts. Rigorous testing of circuits can prevent the shipment of defective parts, but improving the production quality of a circuit depends upon effective failure analysis; that is, the process of determining the cause of detected failures. Discovering the cause of failures in a circuit can often lead to improvements in circuit design or manufacturing processes, with the subsequent production of higher-quality integrated circuits.
Failure analysis usually comprises two tasks: fault diagnosis, which is a logical search to determine the likely sources of error, using circuit information and details about how the circuit failed; and fault location or defect identification, which is a physical search to discover the mechanism of failure in the actual defective part. Given the enormous number of circuit elements in modern ICs, and the number of layers in most complex circuits, physical searches cannot succeed without considerable guidance from fault diagnosis. If the diagnosis is either inaccurate or imprecise (identifying either incorrect or excessively many fault candidates, respectively), the process of fault location will consume, and possibly waste, considerable amounts of time and effort.
Bridging faults, which are defined as the unintentional electrical shorting of two gate outputs, are believed to be a common defect type in integrated circuits and their diagnosis is considered to be crucial in IC manufacturing. A circuit with n nodes has
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possible bridging faults; explicit consideration of all such faults in infeasible. Therefore, a need exists for a fast, accurate and computationally non-complex method for precise diagnosis of bridging faults, particularly with respect to combinational CMOS circuits and full-scan sequential circuits, in which all state elements are controllable and observable. Prior to the present invention, that need has not been met by the conventional diagnostics discussed below.
Fault diagnosis is the logical component of failure analysis; appropriately, its domain is that of the logical fault, or simply fault, which is an abstract representation of how an element in a defective circuit misbehaves. A description of the behavior and assumptions about the nature of a logical fault is referred to as a fault model.
As with testing, diagnosis traditionally involves the choice of a fault model; the most popular fault model for both testing and diagnosis is the single stuck-at fault model, in which a node in the circuit is assumed to be unable to change its logic value. The stuck-at model is popular due to its simplicity, and because it has proven to be effective both in providing test coverage and diagnosing a limited range of faulty behaviors. However, other fault models can be used in diagnosis, and will as be discussed.
The concepts of fault and fault model are separate from that of a defect, which usually refers to the physical mechanism, such as an electrical short or open, that produces the incorrect behavior of the circuit. A logical fault description is an abstract means of representing a defect, an aspect of defect behavior, a class of defects, or several classes of defects. For example, a stuck-at fault is commonly thought to represent the defect of a circuit node being shorted to either power or ground.
While it is common (and convenient) to speak of diagnosis as identifying or locating faults in a circuit, the underlying target of diagnosis is ultimately a physical defect; the fault models used are simply useful abstractions in the eventual identification of a defect or defect location. As will be discussed in the following sections, the association of diagnostic fault model to targeted defect is not inviolable: a diagnosis may be performed using one fault model while e targeting a defect more accurately represented by another fault model.
The traditional method of fault diagnosis, referred to as cause-effect analysis, has been described as test-based fault localization; that is, identification of a defect location by comparing A failures observed on a tester with those predicted in fault simulation. A fault simulator will describe the behavior of a circuit in the presence of a particular instance of a modeled fault, usually in the form of a fault signature. A fault signature is the complete list of all input patterns (or test vectors) and circuit outputs by which a fault is detected. Note, however, that term fault signature is often reserved for only the response of faulty circuits under test. For example, the term fault signature has been defined in the art as the characteristic function of the erroneous response produced by a fault without regard to fault type. In the description herein, however, as in much of common usage, the term signature is applied to actual behaviors, as well as simulated and abstract faults, such as in stuck-at signature and composite signature, which will be introduced later.
The process of test-based fault localization, then, is one of comparing the observed faulty behavior of the circuit with a set of fault signatures, each representing a fault candidate. The resulting set of matches, if any, constitutes a diagnosis.
Many early diagnostic systems used a simple matching process, in which the signature of a fault candidate would either have to match exactly the circuit's fault signature, containing every error-carrying vector and output, or would have to be a subset thereof. As diagnostic techniques matured, the matching process became more flexible; a good example of a simple generalization is known as the partial-intersection operation that ranks matches by the size of intersection. Matching algorithms employed by diagnostic techniques are often essential in translating from abstract fault models to defects, or from targeted fault models to untargeted faults, or to handle the vagaries of faulty circuit behavior.
The following sections describe previous approaches taken to the problem of fault diagnosis. As indicated above, most traditional (cause-effect) techniques involve two primary elements: a fault model, and a comparison or matching algorithm. The approaches described are primarily organized by the fault model used: stuck-at, bridging, or another model. Each technique is presented with a description of the matching algorithm used for diagnosis construction. Subsequent sections discuss other techniques that are not as easily categorized by fault model and matching algorithm.
2.1 Stuck-at fault diagnosis.
Early fault diagnosis systems targeted only stuck-at faults; the fault candidates were stuck-at nodes, and the candidates were described by stuck-at fault signatures. In addition, the actual defect mechanism was interpreted strictly as a single stuck-at circuit node; other defect types could not necessarily be precisely diagnosed.
Many early systems of VLSI diagnosis, such as Western Electric Company's DORA and an early approach of Teradyne, Inc., attempted to incorporate the concept of test-based fault localization with the previous-generation method of diagnosis, called guided-probe analysis. Guided-probe a
Chess Brian
Ferguson F. Joel
Larabee Tracy
Lavo David B.
Moise Emmanuel L.
O'Banion John P.
The Regents of the University of California
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