Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-05-20
2003-11-18
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06651197
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to an apparatus and method for testing logic on circuit chips. In particular, the present invention relates to fabrication of the test logic within the main logic of a chip for partial scan built in self test on a circuit chip.
BACKGROUND OF THE INVENTION
The present trend in integrated circuit design is toward higher levels of circuit integration, thereby reducing costs and improving circuit reliability. As IC technologies continue to develop, it is expected that circuits with at least 100,000,000 devices will become common.
Increased circuit integration is not, however, obtained without drawbacks. Increasing chip testing costs tend to reduce the benefits derived from more economically efficient design and production techniques. The costs associated with integrated circuit chip testing increase in proportion to the number of devices thereon. Much expense is incurred in the development of computer programs for running test routines. The engineering effort and computer time needed to devise these test routines can even exceed the requirements for designing the chip itself. It is not uncommon to employ as many engineers to develop tests for an IC to assure the quality of the part as the number of engineers designing a part. In addition, for particular types of circuits, circuit chip testing costs now account for roughly 10 to 40 percent of the total manufacturing costs.
A testing technique that is becoming, increasingly popular, is the built-in self-test technique. As its name implies, built-in self-test, or BIST, test systems are fabricated on the IC chip to be tested. BIST systems include a pattern or operand generator for producing test operands. Each test operand is applied to the IC logic, and the response thereto analyzed by means of a shift register. The response to thousands, and even millions, of test operands is then compressed into a “signature”, which is compared to predetermined signatures for a go
o go indication of the IC's operation. One such BIST system is disclosed in the Van Brunt U.S. Pat. No. 4,357,703.
The BIST approach to circuit testing offers numerous advantages. BIST has minimal impact upon main logic functions since it is typically fabricated on the sparsely used peripheral areas of the integrated circuit chip. Since test results are processed by the BIST system, the number of tasks which must be performed by external test equipment is reduced. Specially developed maintenance software is therefore greatly reduced. Dynamic testing at full system clock rates significantly reduces system test times. BIST systems can also be used for testing integrated circuits at the wafer, chip, and system levels. Since they are independent of specific chip logic functions, BIST test systems can be used on any number of different types of circuit chips. The BIST approach also permits IC chips to be tested after they have been assembled into a computer, even though they are inaccessible to more traditional maintenance techniques. This will be the case, for example, when the IC is immersed in a liquid coolant to increase its performance.
Even though BIST test systems offer many advantages over alternative techniques, they have yet to be developed to their full potential. BIST testing systems have significant shortcomings when used in integrated circuits having 100,000 or more devices. BIST systems usually generate random numbers as test operands. The quality of many of the test operands, in terms of stressing the part, may be poor. When an integrated circuit has a high number of devices or transistors and as the operand goes deeper and deeper into the logic on the integrated circuit, the test becomes less and less effective. If there is a defect in the integrated circuit at a latch in the middle of the integrated circuit, there is a distinct possibility that the defect may go undetected. Certain areas of the integrated circuit may be untestable in that a defect may not propagate through many layers of logic and to an output pin to cause a test result indicating a defect. The result is that the integrated circuit may test “good” when in fact it is a part with a defect should be scrapped.
One means of alleviating this problem is to incorporate BIST scan circuitry into the inner layers of logic. This scan circuitry provides a means of both stimulating additional activity, and of capturing potentially failing signals that would otherwise be missed.
BIST scan is accomplished by substituting special ‘scan latches ’ for the standard latches contained in the functional logic. These scan latches function the same as a standard latch during normal system operation, but during BIST operations they can behave as both the operand generator and the signature analyzer described above.
In a ‘full scan ’ BIST design, every system latch is actually a scan latch. This provides maximum test coverage, and is simple to design, but uses a great deal of IC resources, and may be too expensive to implement. A popular alternative is ‘partial scan, ’ where only certain key latches get converted to scan latches, selected for maximum impact with the least cost.
Currently, a logic designer converts certain latches of a circuit to scan latches. The logic designer places the scan latches based on his or her experience. The placement of the scan latches is not based on any criteria other than the logic designer's knowledge. The problem is that even an experienced logic designer generally may be unable to place the scan latches so that a significant number of errors are detected. In other words, the scan latches may not be placed where the significant number of errors are detected. Currently, errors are detected and basically counted on a chip wide level.
As a result, there is need for a method and apparatus for determining which of the latches of a logic module should be converted into scan latches. In addition, there is a need for optimizing the placement of the scan latches so that a maximum number of errors can be detected. Furthermore, there is a need for a method and apparatus that does this automatically and one that can be used during simulation of a circuit design.
SUMMARY OF THE INVENTION
An integrated circuit apparatus includes main logic for performing digital logic operations. Also included on the integrated circuit apparatus is testing logic for performing dynamic tests of the main logic. This testing logic enables “Built-In Self Test,” or BIST.
A simulation uses the pseudorandom number generator of the BIST circuitry to test the logic as designed and to convert certain of the latches in the logic to scan latches. The method optimizes the placement of the scan latches so that the maximum number of faults are detected by the scan latches. The system is used in a partial scan integrated circuit which uses a combination of traditional fault simulation and some additional bookkeeping. A logic simulation is run on the logic with single “stuck-at” faults injected into the circuit. While the test is being run, the number of faults detected are maintained in a table or record for every latch in the system. A separate list of faults detected at every scan latch is maintained. This simulation is like having full scan on the logic, based on the data collected and the statistics collected. Certain of the latches are turned into scan latches. For example, the latches having above a certain number of faults may be turned into scan latches, or the latches having any faults may be turned into scan latches. The result is that the particular latches that are turned into scan latches are optimized so that they can catch the most number of faults within the logic. Advantageously, a full scan is no longer necessary and a partial scan will detect most of the faults at the various latches. As a result, the selection of which latches to turn into scan latches is optimized so that it will result in finding the most faults that occur within the system. This minimizes the IC or logic resources needed for a successful test by using partial scan me
O'Neill Edward J.
Wildes Paul T.
De'cady Albert
Schwegman Lundberg Woessner & Kluth P.A.
Silicon Graphics Inc.
Torres Joseph D.
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