Method for detecting a malfunction in a state machine

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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C714S021000, C714S025000, C326S046000

Reexamination Certificate

active

07620868

ABSTRACT:
A method for detecting a malfunction in a state machine is described. The state machine has an operation modeled by a set of states linked to each other by transitions, the state machine generating, upon each transition, output signals according to input signals comprising signals generated during a previous transition. During a transition, the method comprises steps of generating at least one control signal according to a control signal generated during a previous transition, determining an expected value of the control signal, and comparing the control signal with the expected value.

REFERENCES:
patent: 4727548 (1988-02-01), Dickey
Zeng et al., Finite state machine synthesis with concurrent error detection, Sep. 28-30, 1999, IEEE, pp. 672-679.
Leveugle, R. et al., “Alternative Approaches to Fault Detection in FSMs,” International Workshop on Defect and Fault Tolerance in VLSI Systems, Montreal, Canada, Oct. 17-19, 1994, pp. 271-279.
Stojcev, M.K. et al., “VHDL-Based Design of FSM with Concurrent Error Detection Capability,” Proc. 24thInternational Conference on Microelectronics, vol. 2, Nis, Serbia and Montenegro, May 16-19, 2004, pp. 759-762.

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