Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-01-17
2006-01-17
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06988254
ABSTRACT:
A method for designing a semiconductor integrated circuit is provided that is capable of a timing simulation that is approximate to an actual operation by reducing the effect of IR drop on the timing without reducing an effective area necessary for arrangement of elements or the number of pads that can be used other than power supply pads and without increasing the processing time. In a FF driving ability change procedure, a flip-flop having a delay time larger than a transition time from a state in which an IR drop occurs in a power supply voltage to a state of an ideal power supply voltage is substituted for an arbitrary flip-flop. Thus, a delay library considering IR drop may be produced previously only for the flop-flop, thus enabling a production time of the library to be reduced and improving the calculation accuracy of the delay time in the delay calculation procedure. Furthermore, the substitution of a flip-flop having a low driving ability enables the area to be reduced.
REFERENCES:
patent: 6028993 (2000-02-01), Yu et al.
patent: 6090150 (2000-07-01), Tawada
patent: 6099580 (2000-08-01), Boyle et al.
patent: 6216256 (2001-04-01), Inoue et al.
patent: 6405350 (2002-06-01), Tawada
patent: 6453443 (2002-09-01), Chen et al.
patent: 6799310 (2004-09-01), Miyamoto
patent: 6910194 (2005-06-01), Mielke et al.
patent: 2003/0051222 (2003-03-01), Williams et al.
patent: 2004/0054975 (2004-03-01), Yee et al.
patent: 2004/0054979 (2004-03-01), Bobba et al.
patent: 2004/0078767 (2004-04-01), Burks et al.
patent: 2002-73714 (2002-03-01), None
Ishibashi Noriko
Iwanishi Nobufusa
Satoh Kazuhiro
Dimyan Magid Y.
Hamre Schumann Mueller & Larson P.C.
Matsushita Electric - Industrial Co., Ltd.
Smith Matthew
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