Method for designing phase-lock loop circuits

Details Method for designing phase-lock loop circuits Method for designing phase-lock loop circuits

2006-06-20

2008-12-09

Lin, Sun J (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07464346

ABSTRACT:
A method for designing a phase-lock loop (PLL) circuit is disclosed. The method includes the following steps. A first set of intellectual properties, each of which represents a control circuit implemented on a semiconductor substrate, is provided. A second set of intellectual properties, each of which represents a filter implemented on the semiconductor substrate, is provided. Intellectual properties are selected from the first and second sets based on a predetermined specification of the PLL circuit. The selected intellectual properties are integrated as an integrated intellectual property representing the PLL circuit, such that a layout area of the PLL circuit implemented by using the integrated intellectual property is configured based on the predetermined specification.

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