Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-06-04
2003-05-20
Wong, Don (Department: 2821)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06567967
ABSTRACT:
FIELD OF THE INVENTION
This invention generally relates to the design of integrated circuits and more particularly to methods for physically designing very large integrated circuits.
BACKGROUND OF THE INVENTION
There are two basic techniques for physically designing digital integrated circuits (or chips). These are commonly known as the full-custom technique and the standard-cell technique. In the full-custom technique, small blocks (or cells) are manually laid out by hand, one rectangle or polygon at a time to build first transistors, then logic gates, and then more complex circuits. A “block” is a small portion of a design that is designed and/or laid out separately. The cells are assembled together into larger groups (or blocks) which are themselves assembled into still larger blocks until a complete integrated circuit is created. For complex chip designs, this layout and assembly process requires large numbers of highly skilled designers and a long period of time.
The standard-cell technique for designing chips is a much simpler process and has gained wide use. Physical layouts and timing behavior models are created for simple logic functions such as AND, OR, NOT or FlipFlop. These physical layouts are known as “standard cells”. A large group of pre-designed standard cells is then assembled into a standard cell library, which is typically provided at a nominal cost by the fabrication vendor who will eventually produce the actual chip. Examples of these standard cell libraries are available from fabrication vendors such as TSMC or UMC. Automated software tools available from companies such as Cadence Design Systems, Inc. and Synopsys Corp. can take a netlist description of the integrated circuit, or “netlist” representing the desired logical functionality for a chip (sometimes referred to as a behavioral or register-transfer-level description), and map it into an equivalent netlist composed of standard cells from a selected standard cell library. This process is commonly known as “synthesis”.
Other software tools available from companies such as Cadence or Avant! can take a netlist comprised of standard cells and create a physical layout of the chip by placing the cells relative to each other to minimize timing delays or wire lengths, then creating electrical connections (or routing) between the cells to physically complete the desired circuit. The standard cell technique generally produces chips that are somewhat slower and larger than chips designed using the full-custom technique. However, because the process is automated, chips can be designed much more quickly and with fewer people, compared to the full-custom technique. For these reasons, most digital logic chips today are designed using the standard-cell technique.
The standard-cell technique relies heavily on automated software tools to place and route the standard cells. Today, these tools work well with designs that contain less than a few hundreds of thousands of standard cells. The internal algorithms used for placement and routing, however, are non-linear as the size of the design increases. As an illustration, a design containing 500,000 standard cells would take more than twice as long to place and route as a design containing 250,000 standard cells. A design having 500,000 standard cells would also be more than twice as large as a design having 250,000 standard cells, and will run slower. In addition, the available computer memory can be a significant limitation on the maximum size of design that can be created. As a result of these effects, designs above a certain size are not practical to create using the standard-cell approach. Integrated circuit fabrication technology, moreover, has been developing at an exponential rate. A commonly accepted heuristic known as Moore's law states that chip complexity will double every three years.
Some chips being designed today have already reached the point where the standard-cell design technique does not give adequate results, either in terms of development time, chip size or operating speed. This situation will become common in the near future as chip complexity continues to grow. Moreover, in most cases, the full-custom technique is also not practical for designing such large chips because of the inherent long and expensive development process. The full-custom technique is generally used only on very high speed or very high volume designs such as microprocessors where the extra design effort can be offset by higher prices or higher production volumes. Designers have dealt with the limitations of the standard-cell design technique by manually splitting the chip into a number of sections (called place and route units or PRUs) that can then be designed individually using the standard-cell technique.
Splitting the physical chip design into sections allows larger chips to be designed but also creates new design problems relating to how the chip is split into PRUs and how the interactions between PRUs are managed. These problems become intractable for a person to handle manually if there are more than a few PRUs.
Thus, there is a need for an automated design method that will split a large digital integrated circuit design into multiple sections and handle the interactions between sections so that each section can be designed independently and the desired design time, chip size and timing behavior are achieved.
SUMMARY OF THE INVENTION
A method for designing large digital integrated circuits is described. This method consists of several steps, each implemented by a software tool. Most commonly, the steps include those listed below. A particular chip design may not require all of these steps or may have additional steps.
The above and other preferred features of the invention, including various novel details of implementation and combination of elements will now be more particularly described with reference to the accompanying drawings and pointed out in the claims. It will be understood that the particular methods and circuits embodying the invention are shown by way of illustration only and not as limitations of the invention. As will be understood by those skilled in the art, the principles and features of this invention may be employed in various and numerous embodiments without departing from the scope of the invention.
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Frankle Jonathan A.
Greidinger Yaacov I.
Lazaryan Hasmik
Markosian Ara
Reed David S.
Monterey Design Systems, Inc.
Tran Thuy Vinh
Vierra Magen Marcus Harmon & DeNiro LLP
Wong Don
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