Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2007-07-10
2007-07-10
Schillinger, Laura M. (Department: 2813)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S687000
Reexamination Certificate
active
10318606
ABSTRACT:
Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a capping layer and a dielectric layer. The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor. In the process of sputter etching, the capping layer is redeposited onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.
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Clevenger Larry
Dalton Timothy Joseph
Hoinkis Mark
Kaldor Steffen K.
Kumar Kaushik
Blecker Ira D.
Infineon - Technologies AG
Schillinger Laura M.
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