Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2003-04-11
2004-07-20
Gurley, Lynne (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S637000, C438S638000, C438S643000, C438S653000, C438S687000, C438S700000, C438S720000
Reexamination Certificate
active
06764940
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains to methods for forming a metal diffusion barrier on a partially fabricated integrated circuit. The methods employ at least one operation that selectively etches barrier material from the bottom of vias while simultaneously depositing barrier material on most regions of the integrated circuit. The methods are frequently performed on unlanded vias.
BACKGROUND OF THE INVENTION
Integrated circuit (IC) manufacturers have traditionally used aluminum and aluminum alloys, among other metals, as the conductive metal for integrated circuits. While copper has a greater conductivity than aluminum, it has not been used because of certain challenges it presents, including the fact that it readily diffuses into silicon oxide and degrades insulating electrical properties even at very low concentrations. Recently, however, IC manufacturers have been turning to copper because of its high conductivity and electromigration resistance, among other desirable properties. Most notable among the IC metalization processes that use copper is Damascene processing. Damascene processing is often a preferred method because it requires fewer processing steps than other methods and offers a higher yield. It is also particularly well suited to metals such as Cu that cannot readily be patterned by plasma etching.
Damascene processing is a method for forming interconnections on integrated circuits. It involves formation of inlaid metal lines in trenches and vias formed in a dielectric layer (inter-metal dielectric). In order to frame the context of this invention, a brief description of a copper dual Damascene process for forming a partially fabricated integrated circuit is described below. Note that the invention applies to other fabrication processes including single Damascene processes.
Presented in
FIGS. 1A-1F
, is a cross sectional depiction device structures created at various stages of a dual Damascene fabrication process. A cross sectional depiction of a completed structure created by the dual Damascene process is shown in FIG.
2
. Referring to
FIG. 1A
, an example of a typical substrate,
100
, used for dual Damascene fabrication is illustrated. Substrate
100
includes a pre-formed dielectric layer
103
(such as fluorine or carbon doped silicon dioxide or organic-containing low-k materials) with etched line paths (trenches and vias) in which a diffusion barrier
105
has been deposited followed by inlaying with copper conductive routes
107
. Because copper or other mobile conductive material provides the conductive paths of the semiconductor wafer, the underlying silicon devices must be protected from metal ions (e.g., Cu
2+
) that might otherwise diffuse or drift into the silicon. Suitable materials for diffusion barrier
105
include tantalum, tantalum nitride, tungsten, titanium tungsten, titanium nitride, tungsten nitride, and the like. In a typical process, barrier
105
is formed by a physical vapor deposition (PVD) process such as sputtering, a chemical vapor deposition (CVD) process, or an atomic layer deposition (ALD) process. Typical metals for the conductive routes are aluminum and copper. More frequently, copper serves as the metal in Damascene processes, as depicted in these figures. The resultant partially fabricated integrated circuit
100
is a representative substrate for subsequent Damascene processing, as depicted in
FIGS. 1B-1F
.
As depicted in
FIG. 1B
, a silicon nitride or silicon carbide diffusion barrier
109
is deposited to encapsulate conductive routes
107
. Next, a first dielectric layer,
111
, of a dual Damascene dielectric structure is deposited on diffusion barrier
109
. This is followed by deposition of an etch-stop layer
113
(typically composed of silicon nitride or silicon carbide) on the first dielectric layer
111
.
The process follows, as depicted in
FIG. 1C
, where a second dielectric layer
115
of the dual Damascene dielectric structure is deposited in a similar manner to the first dielectric layer
111
, onto etch-stop layer
113
. Deposition of an antireflective layer
117
, typically a silicon oxynitride, follows.
The dual Damascene process continues, as depicted in
FIGS. 1D-1E
, with etching of vias and trenches in the first and second dielectric layers. First, vias
119
are etched through antireflective layer
117
and the second dielectric layer
115
. Standard lithography techniques are used to etch a pattern of these vias. The etching of vias
119
is controlled such that etch-stop layer
113
is not penetrated. As depicted in
FIG. 1E
, in a subsequent lithography process, antireflective layer
117
is removed and trenches
121
are etched in the second dielectric layer
115
; vias
119
are propagated through etch-stop layer
113
, first dielectric layer
111
, and diffusion barrier
109
.
Next, as depicted in
FIG. 1F
, these newly formed vias and trenches are, as described above, coated with a diffusion barrier
123
. As mentioned above, barrier
123
is made of tantalum, or other materials that effectively block diffusion of copper atoms into the dielectric layers.
After diffusion barrier
123
is deposited, a seed layer of copper is applied (typically a PVD process) to enable subsequent electrofilling of the features with copper inlay.
FIG. 2
shows the completed dual Damascene process, in which copper conductive routes
125
are inlayed (seed layer not depicted) into the via and trench surfaces over barrier
123
.
Copper routes
125
and
107
are now in electrical contact and form conductive pathways, as they are separated only by diffusion barrier
123
, which is also somewhat conductive. Traditionally these diffusion barriers are deposited using PVD methods because of the high quality resultant films. However, when depositing in features with higher aspect ratios such as the narrow vias within modern technologies, PVD methods tend to produce films with poor sidewall coverage and thick bottom coverage. To produce films with improved step coverage in vias and trenches, CVD and ALD methods are being considered. However, the bulk resistivity of film using CVD and ALD methods tend to be high, resulting in a high via resistance or poor resistance distribution. Therefore, the common issue to using each of these methods is a high via resistance. In the case of CVD or ALD, it is due to the high bulk resistivity of the film (i.e. >1000 &mgr;&OHgr; cm). In the case of PVD, it is due to high bottom coverage.
Thus, to reduce resistance between the copper routes, a portion of the diffusion barrier may be etched away, specifically at the via bottom, in order to expose the lower copper plug. This approach is generally described in U.S. Pat. No. 6,287,977 to Hashim et al., U.S. Pat. No. 5,985,762 to Geffken et al., and U.S. patent application Ser. No. 09/965,472 filed Sep. 26, 2001, incorporated by reference above. By completely etching away the barrier in the via bottom, the subsequent copper inlay can be deposited directly onto the lower copper line. Conventional methods for etching away diffusion barriers at the bottom of vias (for example, the region of barrier
127
contacting copper inlay
107
in
FIG. 1F
) are problematic in that they are not selective enough. That is, conventional etch methods remove barrier material from undesired areas as well, such as the corners (edges) of the via, trench, and field regions. This can destroy critical dimensions of the via and trench surfaces (faceting of the corners) and unnecessarily exposes the dielectric to plasma. This may lead to dielectric damage, such as critical dimension loss, increase in dielectric constant (with concomitant negative impact on device speed), and poor adhesion to the barrier layer. These problems will be encountered with the method described in the Geffken et al. patent.
Further, when etching through barrier layers and into the underlying copper metal, some copper oxide and etch residues (including polymeric etch residues) are sputtered onto the barrier sidewall. In the unlanded via case, dielectric material is s
Danek Michal
Rozbicki Robert
Beyer Weaver & Thomas LLP
Gurley Lynne
Novellus Systems Inc.
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