Method for defining windows with different etching depths...

Details Method for defining windows with different etching depths... Method for defining windows with different etching depths...

2001-03-12

2003-07-08

Whitehead, Jr., Carl (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S049000, C438S620000, C438S695000, C438S700000, C438S702000

Reexamination Certificate

active

06589864

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method for defining windows with different etching depths simultaneously, and more particularly to one for used in the process of the thin film transistor.
BACKGROUND OF THE INVENTION
For the structure of the currently developed thin film transistor liquid crystal display (TFT-LCD), the cross sectional view thereof is generally as shown in FIG.
1
. The structure includes a gate conducting layer
11
, a gate insulating layer
12
, high doping semiconductor layer
13
, a data conducting layer
14
and a passivation
15
, which are formed in order from bottom to top on a glass substrate
10
. All these layers are essential. In addition, for electrically connecting the structure to the peripheral control circuits, a first contact window
16
is etched to connect to the gate conducting layer
11
and a second contact window
17
is etched to connect to the data conducting layer
14
, and then a transparent electrode layer
18
is covered thereon for achieving electricity.
Generally, the first contact window
16
and the second contact window
17
are formed with the same photo mask by a photolithography etching process. However, the depths of two contact windows
16
,
17
are different. The first contact window
16
has to pass through the passivation
15
and the gate insulating layer
12
to reach the gate conducting layer
11
, while the second contact window only has to pass through the passivation
15
to reach the data conducting layer
14
. Therefore, forming the two contact windows
16
and
17
having different depths at the same time needs an excellent processing control technology. In other words, the improper processing control will cause the insufficiently etched depth of the first contact window
16
or the over etched depth of the second contact window
17
. The insufficiently etched depth of the first contact window
16
usually results in a bad electrical connection because partially the gate insulating layer
12
is remained. The over etched depth of the second contact window
17
also affects the electrical properties, because the structure in the vicinity thereof is damaged, the under cut condition is happened, or the data conducting layer
14
is damaged. Therefore, the purpose of the present invention is to develop a method to deal with the above situations encountered in the prior art.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to propose a method for defining plural windows with different etching depths of a multiple film structure simultaneously to avoid the bad electrical connection.
It is therefore another object of the present invention to propose a method for defining plural windows with different etching depths of a multiple film structure simultaneously to avoid the structure in the vicinity thereof damaged.
It is therefore an additional object of the present invention to propose a method for defining plural windows with different etching depths of a multiple film structure simultaneously to avoid the under cut condition happened.
It is therefore a further object of the present invention to propose a method for defining plural windows with different etching depths of a multiple film structure simultaneously to avoid the data conducting layer damaged.
It is therefore a yet object of the present invention to propose a method for defining plural windows with different etching depths of a multiple film structure simultaneously to increase the flexibility of the process and the yield of the product.
According to the present invention, the method for defining plural windows with different etching depths simultaneously includes steps of (a) forming a photoresist on a substrate having a multiple film structure thereon, (b) exposing a first region of the photoresist to a first exposure dose and a second region of the photoresist to a second exposure dose, (c) obtaining different remaining thickenesses of the photoresist on the first region and the second region by a development, and (d) etching the first region and the second region of the photoresist for forming the plural windows with different etching depths of the multiple film structure.
Certainly, the substrate can be an insulating substrate. The insulating substrate is preferably a transparent glass substrate and the multiple film structure is a thin film transistor circuit structure.
Certainly, the thin film transistor circuit structure can include a gate conducting layer, a gate insulating layer formed on the gate conductor layer, a high doping semiconductor layer formed on the gate insulating layer, a data conducting layer formed on the high doping semiconductor layer, and a passivation formed on the data conducting layer.
Certainly, the step (d) can include steps of non-selectively etching the first region and the second region simultaneously, and forming a first contact window connected to the gate conducting layer of the thin film transistor structure on the first region, and a second contact window connected to the gate conducting layer of the thin film transistor structure on the second region in response to the different remaining thickenesses of the photoresist.
When the first region of the photoresist has the remaining thickness of zero, the step (d) can include steps of performing a first selective etching of the first region and the second region, thereby allowing an exposure portion of the passivation of the first region to be etched and causing the second region covered by the photoresist unable to be etched, then performing a second selective etching of the first region and the second region, wherein the second region having the remaining photoresist is etched to expose the passivation, and then performing a third selective etching of the first region and the second region, wherein the first contact window connected to the gate conducting layer of the thin film transistor structure on the first region and the second contact window connected the gate conducting layer of the thin film transistor structure on the second region are formed.
Preferably, the step (b) include steps of providing a photo mask having a first penetrable region and a second penetrable region respectively corresponding to the first region and the second region of the photoresist, wherein the first penetrable region has a higher light-penetrability rate relative to that of the second penetrable region, and exposing the photoresist of the multiple film structure to an identical exposure dose for obtaining the first exposure dose and the second exposure dose by the photo mask with two different light-penetrability rates.
Preferably, the first penetrable region is a complete transparent region. The second penetrable region is an optical compensation film for blocking a portion of exposure dose to pass therethrough.
Certainly, the second penetrable region can be plural array mask patterns for blocking a portion of exposure energy to pass therethrough and resulting in a diffraction by a light which pass through the plural array mask patterns.
The present invention may best be understood through the following description with reference to the accompanying drawings, in which:


REFERENCES:
patent: 5741624 (1998-04-01), Jeng et al.
patent: 5976968 (1999-11-01), Dai
patent: 0220578 (1986-10-01), None
patent: 63230889 (1988-09-01), None
patent: 8279488 (1996-10-01), None

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