Method for defect reduction for memory cell capacitors

Details Method for defect reduction for memory cell capacitors Method for defect reduction for memory cell capacitors

2008-10-27

2011-11-08

Chen, Jack (Department: 2893)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S396000, C257SE21008

Reexamination Certificate

active

08053310

ABSTRACT:
A method for forming a cylindrical stack capacitor structure. A semiconductor substrate is provided. Storage node structures are formed in a memory cell region. A dielectric layer is formed overlying the storage node structures. A patterning and a first etching process expose the storage nodes. A polysilicon layer and a rugged polysilicon layer are formed overlying the exposed storage nodes. The memory cell region is masked, exposing a peripheral region. A chemical dry etch process removes the rugged polysilicon and the polysilicon layers in the peripheral region. The rugged polysilicon and the polysilicon layers are planarized followed by a dielectric recess. The resulting cylindrical stack capacitor structures are substantially free of defects from rugged polysilicon remaining in the peripheral region thereby improving device yield and process window.

REFERENCES:
patent: 2010/0003794 (2010-01-01), Jin et al.

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