Method for creation of a very narrow emitter feature

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S309000

Reexamination Certificate

active

06858485

ABSTRACT:
A double-polysilicon, self-aligned bipolar transistor has a collector region formed in a doped semiconductor substrate, an intrinsic counterdoped base formed on the surface of the substrate and a doped emitter formed in the surface of the intrinsic base. Form an etch stop dielectric layer over the intrinsic base layer above the collector. Form a base contact layer of a conductive material over the etch stop dielectric layer and the intrinsic base layer. Form a second dielectric layer over the base contact layer. Etch a wide window through the dielectric layer and the base contact layer stopping the etching of the window at the etch stop dielectric layer. Form an island or a peninsula narrowing the wide window leaving at least one narrowed window within the wide window. Form sidewall spacers in the either the wide window or the narrowed window. Fill the windows with doped polysilicon to form an extrinsic emitter. Form an emitter below the extrinsic emitter in the surface of the intrinsic base.

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patent: 6440810 (2002-08-01), Johansson et al.
patent: 6475848 (2002-11-01), Darwish et al.
Greg Freeman et al., “SiGe HBT Performance and Reliability Trends through fT of 350GHz, ” Proc. IEEE Reliability Physics Symposium (Mar. 30, 2003).
Mathias Rickelt et al., “Influence of Impact-Ionization Induced Instabilities on the Maximum Usable Output Voltage of Si-Bipolar Transistors,” IEEE Trans. on Electron Devices Vo. 48 n. 4 p. 774-783 (Apr. 2001).

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