Method for creating tensile strain by selectively applying...

Details Method for creating tensile strain by selectively applying... Method for creating tensile strain by selectively applying...

2011-03-01

2011-03-01

Landau, Matthew C (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S305000, C257SE21634

Reexamination Certificate

active

07897451

ABSTRACT:
By selectively applying a stress memorization technique to N-channel transistors, a significant improvement of transistor performance may be achieved. High selectivity in applying the stress memorization approach may be accomplished by substantially maintaining the crystalline state of the P-channel transistors while annealing the N-channel transistors in the presence of an appropriate material layer which may not to be patterned prior to the anneal process, thereby avoiding additional lithography and masking steps.

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Wei et al., “Multiple Stress Memorization in Advanced SOI CMOS Technologies,” 2007Symposium on VLSI Technology Digest of Technical Papers, pp. 216-217, 2007.
Translation of Official Communication from German Patent Office for German Patent Application No. 10 2007 057 687.2 dated Aug. 12, 2008.

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