Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-04-20
2002-04-30
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S202000, C257S378000, C257S394000
Reexamination Certificate
active
06380022
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to metal oxide semiconductor (“MOS”) devices. More particularly, the present invention relates to a method for creating a useful bipolar junction transistor (“BJT”) from a parasitic BJT on a MOS device.
BACKGROUND
Because of the pn junctions which are created in the manufacture of MOS devices, a parasitic BJT is formed during manufacture of a MOS field effect transistor (“FET”). The parasitic BJT is connected in parallel to the MOSFET, because emitter, base and collector of the BJT are formed from the source, channel and drain, respectively, of the MOSFET. The parasitic BJT is formed from the “n” and “p” type materials that are used in the different regions of the MOSFET. That is, an n-channel MOSFET would have a parasitic npn-type BJT associated with it and a p-channel MOSFET would have an associated parasitic pnp-type BJT.
The parasitic BJT may create unwanted effects during the operation of the MOS device. Because the base of the parasitic BJT is electrically connected to the channel of the MOSFET, it is floating and the device is more difficult to control. A floating base causes a history dependent delay, which changes the MOS characteristics. This is particularly a problem with silicon-on-insulation (“SOI”) MOS field effect devices, because the channel of the MOSFET is isolated from the substrate, as explained further herein (e.g., see FIG.
2
).
The manufacturing process for MOSFETs currently requires steps designed to nullify the effect of the parasitic BJT. Clearly, a method that would transform the parasitic BJT into a useable BJT would be desirable.
SUMMARY
One embodiment of the present invention relates to a method for creating a useful BJT by increasing the gain associated with the parasitic BJT on an SOI or bulk type MOSFET to a desired level. Once the gain is increased sufficiently, the BJT may be used productively in the circuit by driving the base of the BJT with the circuit. Because the physical structure of the BJT is already part of the silicon wafer, its Productive use does not require additional space.
One embodiment of the MOS device of the present invention comprises a useful BJT that is formed from a parasitic BJT, connected in parallel to the MOS device
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patent: 440331 (1991-08-01), None
Colinge, “An SOI Voltage-Controlled Bipolar-MOS Device,” IEEE Transaction on Electron Devices, vol. ED-34, No. 4, Apr. 1987, pp. 845-849.
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