Method for controlling transistor spacer width

Details Method for controlling transistor spacer width Method for controlling transistor spacer width

2000-01-20

2000-10-17

Bowers, Charles

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438 14, H01L 213205, H01L 214763

Patent

active

061331325

ABSTRACT:
A method for controlling spacer width in a semiconductor device is provided. A substrate having a gate formed thereon is provided. An insulative layer is formed over at least a portion of the substrate. The insulative layer covers the gate. The thickness of the insulative layer is measured. A portion of the insulative layer to be removed is determined based on the measured thickness of the insulative layer. The portion of the insulative layer is removed to define a spacer on the gate. A processing line for forming a spacer on a gate disposed on a substrate includes a deposition tool, a thickness metrology tool, and automatic process controller, and a spacer etch tool. The deposition tool is adapted to form an insulative layer over at least a portion of the substrate. The insulative layer covers the gate. The thickness metrology tool is adapted to measure the thickness of the insulative layer. The automatic process controller is adapted to determine a portion of the insulative layer to be removed based on the measured thickness of the insulative layer. The spacer etch tool is adapted to remove the portion of the insulative layer to define a spacer on the gate.

REFERENCES:
patent: 4855247 (1989-08-01), Ma et al.
patent: 5093273 (1992-03-01), Okumura
patent: 5856224 (1999-01-01), Sheu
patent: 5863824 (1999-01-01), Gardner et al.

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