Method for controlling etch bias of carbon doped oxide films

Details Method for controlling etch bias of carbon doped oxide films Method for controlling etch bias of carbon doped oxide films

2002-06-10

2003-09-16

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S780000, C438S689000, C438S711000, C438S733000, C438S790000, C438S793000, C438S794000, C349S001000, C349S002000, C427S447000, C427S255140, C257S040000

Reexamination Certificate

active

06620741

ABSTRACT:

BACKGROUND
One of the trends in the manufacture of semiconductor devices is to shrink the size of the semiconductor devices. Therefore, the size of components (e.g., trenches vias, contacts, interconnect lines, plugs etc.) that form the semiconductor devices have correspondingly continued to shrink. This results in an increase in the density of the components that form the semiconductor devices. Today, semiconductor devices are manufactured with the components having submicron dimensions, necessitating the routine fabrication of submicron structures such as trenches and vias.
Due to the smaller size of semiconductor devices and the increased density of the components that form the semiconductor device it is essential to control the critical dimensions (CDs) of the components. The CD of a component is the dimension of a specified geometry that must be within design tolerances. The CD may represent the width of a patterned line or the distance between two lines necessary to maintain the semiconductor device's performance consistency. If the CDs of the components are not controlled, the components may not perform according to design specifications (e.g., due to a change in resistivity, capacitance or other electrical specifications) resulting in a degradation of the performance of the semiconductor device, or even in a catastrophic failure of the semiconductor device.
In order to control the CD of the components, the process used to manufacture the components should control at least the etch bias. Etch bias is the difference between the desired dimension patterned after photolithography, and the dimension of the component actually formed after etching. For example, if the desired width of a trench is 1 &mgr;m (patterned after photolithography) and if the process used to manufacture the trench etches a 1.30 &mgr;m trench, then the process is said to have an etch bias of ±0.3 &mgr;m. Having a poor etch bias is undesirable as the CD of the component may not be maintained, resulting in a possible degradation and/or failure of the semiconductor device.
FIGS. 1A-1C
illustrate a prior art process used to etch a trench in a dielectric layer of a semiconductor device. One having ordinary skill in the art will appreciate that components e.g., trenches and vias may be used in dual damascene integration of copper interconnects, and the dielectric layer insulates the copper interconnect lines, vias, contacts, etc. As illustrated in
FIG. 1A
, a semiconductor device
100
comprises a carbon doped oxide (CDO) dielectric layer
110
. The CDO dielectric layer
110
is a compound comprising SiO
2
, C, and H, and may be deposited by any one of a variety of methods (e.g., chemical vapor deposition, by spinning the CDO on a wafer etc.). A photoresist layer
120
is deposited on top of the dielectric layer
110
. The photoresist layer has a window
130
having a width equal to the CD of the width of the trench. In a positive resist technique, the photoresist layer
1
20
is exposed to light and developed in a developing solution to remove the portions of the photoresist layer that are exposed to light. Therefore,
FIG. 1A
illustrates the photoresist layer
1
20
after the portion of the photoresist layer that is exposed to light is removed. One having ordinary skill in the art will appreciate that negative resist techniques may also be used to etch components e.g., trenches, vias etc.
FIG. 1B
illustrates the semiconductor device
100
after the CDO dielectric layer has been subjected to a plasma etch process. The plasma etch process comprises exposing the semiconductor device
100
to a plasma comprising a carbon fluorine gas (e.g., C
4
F
8
, C
2
F
6
, or CF
4
), oxygen or nitrogen, and argon in a reactor. The plasma is struck at radio frequency (RF) power in the range of 1000-4000 Watts. The plasma etch process is anisotropic and a trench
135
is formed after the semiconductor device
100
is subjected to the plasma in the reactor for a predetermined time period. Due to the reaction of the plasma, and in particular the oxygen in the plasma with the organic carbon containing species CH
3
etc. in the sidewalls of the trench
135
, gasses e.g., carbon dioxide and carbon monoxide are released. The depletion of organic carbon containing species from the sidewalls of the CDO dielectric layer
110
results in a depletion region
140
. The depletion region
140
is silica like and is easily stripped by fluoride ion containing reagents that are used during the wet clean process.
FIG. 1C
illustrates semiconductor device
100
after the wet clean process. As illustrated in
FIG. 1C
, the ashing or wet clean process removes the photoresist layer
120
. In addition, the wet clean process removes the depletion region
140
and causes the width of the trench to be larger than the CD of the trench (CDO blow out). Having a trench width larger than the CD of the trench is undesirable. If the depletion region
140
is left in place and not removed by the wet clean process, the dielectric constant ‘k’ of the depletion region is increased. This increase in the dielectric constant results in the dielectric layer being less effective as an insulating material, and results in undesirable capacitive cross-talk between adjacent copper lines.


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