Method for controlling data output buffer for use in operation a

Details Method for controlling data output buffer for use in operation a Method for controlling data output buffer for use in operation a

1996-09-11

1998-11-10

Dinh, Son T.

Static information storage and retrieval

Addressing

Sync/clocking

36518905, G11C 700

Patent

active

058354441

ABSTRACT:
Methods and apparatus for controlling output buffer circuitry in a synchronous semiconductor memory device. An internal clock signal is generated and logic provided to provide a control signal that enables that output buffer circuitry for a read operation. An internal clock signal is generated synchronized to the external or system clock signal. An intermediate control signal is triggered by the internal clock signal at a selected number of cycles less than the memory latency period after a read command, and then the control signal for enabling the output buffer is asserted on a subsequent cycle of the internal clock signal, thereby ensuring at least a predetermined minimum time for the output buffer control signal to propagate through the memory device before data is transferred out of the device.

REFERENCES:
patent: 5324993 (1994-06-01), Ikawa
patent: 5384750 (1995-01-01), Lee
patent: 5402388 (1995-03-01), Wojcicki et al.
patent: 5535171 (1996-07-01), Kim et al.

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