Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
1999-05-28
2002-09-24
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
C713S001000, C713S500000, C713S600000, C709S241000, C710S058000
Reexamination Certificate
active
06457137
ABSTRACT:
FIELD OF INVENTION
The present invention relates to microprocessors. More specifically, it relates to the configuration of a clock ratio for a microprocessor at power-up.
BACKGROUND OF THE INVENTION
Operations in a microprocessors are typically driven by a clock signal which allows the internal operations of the microprocessor to be coordinated with external events.
FIG. 1
is a simplified block diagram of one embodiment of a typical microprocessor
100
.
Microprocessor
100
includes an instruction cache
110
that contains microcoded instructions that control the operation of instruction sequencer
112
. Sequencer
112
, in turn drives the functional units of processor
100
by generating CONTROL signals onto internal control bus
140
and, when needed, outputting CONSTANTS to execution and address generator unit
144
.
The CONTROL signals generated by sequencer
112
and distributed through control bus
140
control and coordinate the operation of the functional units inside processor
100
. These functional units are register file
130
, multiplication and division unit
142
, execution and address generation unit
144
, memory interface unit
146
, bus control unit
170
and local data cache
180
.
Register file
130
is used to store operand and result data within processor
100
. Internal bus
150
represents three independent busses, first and second source busses and a destination bus, for transferring operands to the multiplication and division unit
142
and the execution and address generation unit
144
from the register file and the results of the operations of these units back to register file
130
. In addition, memory interface unit
146
transfers address and data values between internal data and address bus
160
and internal source and destination bus
150
and receives address values from execution and address generation unit
144
.
Bus control unit
170
coordinates the transfer of control, address and data information between internal bus
160
and external busses
30
,
40
and
50
. Control signals are output to units peripheral to processor
100
via control bus
30
. Address values are output to peripheral units, such as memory subsystems and disc controllers, via address bus
40
. Instructions and operands data are transferred into and out of processor
100
via data bus
50
. The address bus
40
and data bus
50
typically interface with a system bus, such as a host bus that interfaces between the processor
100
and a chipset, such as a bus bridge or cache controller. The host bus typically operates at a different frequency from internal busses
150
and
160
that is determined by external clock signal CLK.
The external clock signal CLK is input to processor
100
via external interface pin
20
. The external clock signal CLK is typically the timing signal that coordinates the activity on the external busses CONTROL BUS
30
, ADDRESS BUS
40
and DATA BUS
50
that interface with processor
100
. The CLK signal is input to a clock and power management unit
120
that typically multiples the frequency of the CLK signal in order to generate a higher speed internal clock signal INCLK that coordinates the activity of the function units and busses inside processor
100
. The connection of INCLK to each of the function units is omitted from
FIG. 1
in the interest of clarity.
The CONTROL signals generated by sequencer
112
are thus coordinated by the internal clock signal INCLK. This permits the internal operations of processor
100
to execute at a faster rate than the external events, such as data and instruction transfers via the external busses
30
,
40
and
50
. The ratio of the frequency of the internal clock signal INCLK to the frequency of the external clock signal CLK is the microprocessor's clock ratio. For example, with an external clock frequency for CLK of 50 MHz and a clock ratio of four, the processor will run internally at 200 MHz.
One method for the processor to determine its clock ratio is, when the processor
100
is coming out of a reset event, it will sense a set of signal lines BF
0
, BF
1
and BF
2
as clock configuration lines that determine the clock ratio of the processor. Conventionally, the values on these clock configuration lines BF
0
-
2
are determined through the use of hardware, such as resistors or jumpers, to place the correct logic value voltages on the relevant clock configuration lines. In many processors, if these lines are left unconnected, then the clock ratio defaults to a predetermined default value, such as ½ or ⅔.
The values on the external pins BF
0
-
2
are typically sampled at processor reset and cannot be changed until another processor reset event occurs, e.g. a reset pin of the processor is asserted. Further, the value on pins BF
0
-
2
typically cannot be changed when reset is active. Changing the clock ratio requires that the values on pins BF
0
-
2
be physically changed and then the processor reset. For more detailed information on a particular processor, see the Embedded Pentium Processor Family Developer's Manual from Intel at developer.intel.com/design.
This hardware approach is inflexible. Changing the clock ratio is a cumbersome and disruptive process that requires physical access to the motherboard or processor chip. In many cases, in particular embedded processor designs, there is no physical access to the clock configuration pins BF
0
-
2
once the processor has been incorporated into a product. Therefore, the need remains for a convenient and flexible way to change the clock ratio of a processor.
SUMMARY OF THE INVENTION
In accordance with preferred embodiments of the present invention, some of the problems associated with configuring the clock ratio of a processor are overcome.
An embodiment of a method, according to the present invention, for changing the clock ratio of a processor under software control includes, responsive to reset of the processor, reading a first bit pattern present on clock ratio configuration pins of the processor and booting the processor with a clock ratio corresponding to the bit pattern present on the clock ratio configuration pins. The method then calls for comparing the clock ratio of the processor after booting to a desired clock ratio value from a non-volatile storage. Then, when the clock ratio of the processor after booting does not equal the desired clock ratio value, writing the desired value to a register coupled to the clock ratio configuration pins of the processor and inhibiting reset of the register. The method then requires resetting the processor when the clock ratio of the processor after booting does not equal the correct clock ratio value.
The foregoing and other features and advantages of a preferred embodiment of the present invention will be more readily apparent from the following detailed description, which proceeds with references to the accompanying drawings.
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Embedded Pentium® Processor FamilyDeveloper's Manual, Chapter 16.10 Fractional Speed Bus, Intel®, 1998, pp. 16-218 to 16-221.
Pentium® Processor FamilyDeveloper's Manual, Chapter 5.1.10. Hardware Interface, BF1-0, Intel®,1997, pp. 5-17 to 5-18.
D'Souza Christian A.
Dempsey Michael P.
Mitchell Craig G.
Pandey Chandra S.
3Com Corporation
McDonnell & Boehnen Hulbert & Berghoff
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