Method for conditioning a plasma etch chamber

Etching a substrate: processes – Gas phase etching of substrate – Application of energy to the gaseous etchant or to the...

Reexamination Certificate

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C438S905000

Reexamination Certificate

active

06322716

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor fabrication and, more particularly, to a method for conditioning plasma etch chambers in which, e.g., a cover topography is positioned upon a chuck within the chamber and a conditioning plasma is generated such that the thickness of the cover topography immediately after generating the conditioning plasma is at least as great as the thickness of the cover topography immediately before generating the conditioning plasma.
2. Description of the Related Art
The information described below is not admitted to be prior art by virtue of its inclusion in this Background section.
Conditioning processes are commonly implemented in semiconductor fabrication to prepare plasma chambers for the optimal performance of plasma processes. When used with plasma etch chambers, conditioning processes typically involve generating a conditioning plasma in the plasma chamber for a predetermined length of time to prepare, or “season”, the chamber for the performance of etch processes with production wafers. The parameters of the conditioning process (e.g., RF power, feed gas composition, and pressure) are usually maintained at or near the parameters of the corresponding etching process for which the chamber is being conditioned. In this manner, conditioning processes can help ensure that all etch processes performed in an etch chamber produce results within a desired range.
One important way that plasma etch chamber conditioning processes help prepare an etch chamber for etch processing is through the deposition of polymeric material on plasma chamber inner surfaces. Plasma etch processes often use a variety of (hydro)halocarbons as etchants. The particular class of (hydro)halocarbon selected generally depends on the material being etched. For example, (hydro)fluorocarbon plasmas are commonly used to etch dielectric materials such as silicon dioxide. By using certain combinations of etchant gases (with other gases, such as inert gases, potentially mixed in), materials on the upper surface of a semiconductor topography (i.e., a semiconductor substrate and any overlying materials) can be etched. While etching plasmas formed from (hydro)halocarbons can etch material on the upper surface of a semiconductor topography, such plasmas often concurrently deposit thin layers of polymeric material on the relatively colder (in relation to the upper surfaces of the semiconductor topography being processed) inner surfaces of the plasma chamber, such as the etch chamber inner walls. Since plasma etch chamber conditioning plasmas are usually generated under similar conditions as a corresponding etching plasma, the conditioning plasmas can be used to deposit layers of polymeric material having a similar composition to the polymeric material deposited over the course of normal etch processing.
The ability of plasma etch chamber conditioning processes to deposit polymers on chamber inner surfaces is particularly important when conditioning an etch chamber after cleaning. Plasma etch chambers are periodically cleaned to remove contaminants that collect on the inner surfaces of the etch chamber during processing. Cleaning of such chambers may be carried out using wet cleaning processes (i.e., processes that use liquid etchants to remove materials from the chamber inner surfaces) or dry cleaning processes (i.e., processes that use plasmas to remove materials from the chamber inner surfaces). Regardless of the type of cleaning process used, trace residues of the chemicals used in the cleaning process may remain on the chamber inner surfaces after cleaning. By performing conditioning processes, layers of polymeric materials may be deposited on the chamber inner surfaces that serve to trap these residues, as well as other contaminants, and thus reduce contamination during subsequent processing.
Conditioning processes may also be used to replace the deposited polymeric films removed during cleaning and thus improve initial plasma behavior in subsequent etch processing. The deposited polymeric films may act as insulators, and thus can affect the coupling condition of plasmas formed therein. In addition to removing contaminants that have accumulated within an etch chamber during processing, however, cleaning processes also remove the polymeric films deposited on the chamber inner surfaces. Since the etch process parameters are typically designed to account for the insulating effects of these polymeric layers, any etch processes performed in the absence of such layers may not produce the desired results (e.g., because of direct coupling of the plasma to the chamber walls). Conditioning processes performed after cleaning may be used to deposit a polymeric layer having insulating properties similar to the polymeric layers deposited during normal processing and sufficiently thick to help ensure that the plasmas formed in subsequent etch process behave as intended.
Conditioning processes may also be used to heat-up the inner surfaces of an etch chamber after an extended idle period (or first use). Generally speaking, plasma etch processes are typically performed on several wafers or sets of wafers in a series of sequential process steps. Processing of production wafers does not continue indefinitely, however, but may instead be periodically halted for numerous reasons, including cleaning processes, repairs, and simple idle time. During such intermissions, the inner surfaces of the chamber may cool. If etch processing is resumed or initiated in a chamber having inner surfaces substantially cooler than during normal processing, the initial etching performance may be sub-optimal. To overcome such problems, relatively shorter conditioning processes may be use to elevate the temperature of the inner surfaces of the plasma chamber to levels at or near the temperatures of the inner surfaces during normal processing. In this manner, conditioning processes may improve the initial performance of an etch process after an extended idle period.
One way in which plasma etch chamber conditioning processes differ from regular etch processes is that the chuck is typically covered by a dummy wafer instead of by a production wafer as in normal etch processes. It is generally undesirable for reactive species (whether generated from a conditioning plasma or from a normal etching plasma) to contact the upper surface of a chuck. While the upper surface of the chuck is covered by a production wafer during normal processing, production wafers are usually not left within a chamber during chamber conditioning. Consequently, a dummy wafer is used to cover the chuck while conditioning is performed.
Generally speaking, a dummy wafer is a wafer used in place of a production semiconductor wafer during a process step but from which semiconductor devices are not produced. Dummy wafers are typically devoid of preformed patterns and have substantially planar upper surfaces. A variety of dummy wafer types may be used in semiconductor processing, including ceramic wafers (e.g., aluminum oxide and aluminum nitride wafers) and silicon wafers (e.g., oxide-coated, photoresist-coated, and bare silicon wafers). Because of their relatively lower cost, ceramic and bare silicon or oxide-covered silicon wafers are commonly used in plasma enhanced deposition chambers. Since PECVD processes deposit materials instead of etching them, concern about the particular materials of which the dummy wafers are constructed is more limited. Consequently, a variety of dummy wafer types may be freely used in plasma enhanced deposition chamber conditioning processes for plasma enhanced deposition chamber, even when the conditioning processes closely replicate deposition conditions.
Unfortunately, plasmas formed in conventional etch chamber conditioning processes can etch the upper surface of the dummy wafers, limiting the types of wafers that can be used as dummy wafers and increasing the cost and complexity of the conditioning process. For example, if bare silicon dummy wafers are used to cover the chuck

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