Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-07-07
2004-10-19
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S278000
Reexamination Certificate
active
06806142
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates generally to a method for manufacturing read only memory (ROM) devices. More specifically, a method is disclosed for shortening the product turn-around time for making semiconductor permanent store ROM by ROM coding the memory in a late stage. Instead of threshold voltage implantation, the present invention uses deep trench etching to implement ROM cell coding.
2. Description of the Prior Art
Read-only memory (ROM), also known as firmware, is an integrated circuit programmed with specific data when it is manufactured. ROM chips are used not only in computers, but in most other electronic items as well. The process of programming data is also referred to as coding. Hitherto, numerous coding methods have been developed to program data into the memory cells during different phases of their manufacture. One development that has gained wide use is the threshold voltage implant method, which changes a transistor's threshold voltage by ion implanting the transistor gates for programmed cells. By way of example, for coding an N-channel memory cell, a predetermined dosage of impurities such as boron are implanted into the channel area under the gate of the transistor to raise its threshold voltage, thereby turning this memory cell into an “off” state. Another coding method includes selectively opening the contact holes for each transistor to drain. Such method, which is also known as the through-hole contact programming technique, requires a contact for every cell, thereby increasing the size of the cell array.
It is often desirable to apply the ROM code onto the partially completed devices during a latter part of the manufacturing process. By applying the code at the latter part of the process, it takes less time to complete wafer processing. Customers require the product turn-around time between reception of the ROM code for a custom order and delivery of finished parts to be kept as short as possible. Less time for completion means a shorter product turn-around time.
U.S. Pat. No. 4,268,950, filed Jun. 5, 1978 by Chatterjee et al., assigned to Texas Instruments discloses a process for making an N-channel silicon gate MOS read only memory that may be programmed -at a late stage in the manufacturing process. The cell array is programmed by boron implantation through a protective nitride, polysilicon strips, and gate oxides to raise the threshold voltage of selected cells to a value above that which will be turned on by the voltage on the selected address line. U.S. Pat. No. 5,514,609, filed May 13, 1994 by Chen et al., assigned to Mosel Vitelic discloses the manufacture of a ROM cell that is coded before metallization. ROM code impurities are implanted first through a dielectric layer overlying gate electrodes, and then through the underlying selected gate electrodes.
U.S. Pat. No. 6,020,241, filed Dec. 22, 1997 by You et al., assigned to Taiwan Semiconductor Manufacturing Company discloses a method of manufacturing a ROM that is code implanted late in the process after the first level metal thus reducing the turn-around time to ship a customer order. The code implantation implants impurities through a first dielectric layer overlying gates and a second dielectric layer overlying the first dielectric layer, and through a portion of the word lines.
SUMMARY OF INVENTION
It is therefore a primary objective of this invention to provide a method for manufacturing high-density read only memory (ROM) devices, thereby shortening the product turn-around time.
Briefly summarized, the preferred embodiment of the present invention discloses a method for manufacturing a read only memory (ROM) device capable of shortening product turn-around time. A semiconductor substrate having thereon an array of metal-oxide-semiconductor field-effect transistors (MOSFETS) within a ROM region is provided. A dielectric layer covers the MOSFETs within the ROM region. Each of the MOSFETs has a gate, a source, and a drain. All of the MOSFETs are initially in an “ON” state. The method comprises forming a coding photoresist layer on the dielectric layer. The coding photoresist layer is then patterned to form a plurality of apertures defining exposure windows where the underlying MOSFETs are to be coded from the “ON” state into an “OFF” state. The exposure windows are disposed above the sources of the MOSFETs to be coded. An etching process is carried out, using the patterning coding photoresist layer as an etching hard mask, to etch the dielectric layer, the sources of the MOSFETs to be coded, and a portion of the semiconductor substrate underneath the sources of the MOSFETs to be coded through the exposure windows to a depth that is lower than a junction depth of the sources of the MOSFETs to be coded, to form a deep trench that disconnects the sources of the MOSFETs to be coded from source lines. The coding photoresist layer is stripped. A gap fill layer is deposited over the dielectric layer to fill the deep trench.
According to the claimed invention, a method for manufacturing a read only memory (ROM) device is disclosed. A semiconductor substrate having thereon an array of field-effect transistors within a ROM region and a first dielectric layer covering the array of field-effect transistors is provided. Each of the MOSFETs. has a gate, a drain, and a source connected to a source line. All of the field-effect transistors are initially in an “ON” state. The method comprises forming bit lines on the first dielectric layer within the ROM region. The bit lines are covered by a second dielectric layer. The bit lines bypass the underlying sources of the array of the field-effect transistors to not overlap with the sources. A coding photoresist layer is formed on the second dielectric layer. The coding photoresist layer is then patterned to form a plurality of apertures defining exposure windows where the underlying field-effect transistors are to be coded permanently to an “OFF” state. A code etching back process is implemented using the patterning coding photoresist layer as an etching hard mask to etch the second dielectric layer, the first dielectric layer, the sources of the MOSFETs to be coded, and a portion of the semiconductor substrate underneath the sources of the MOSFETs to be coded through the exposure windows to a depth that is lower than a junction depth of the sources of the MOSFETs to be coded, so as to form a deep trench, which disconnects the sources of the MOSFETs to be coded from the source lines. The coding photoresist layer is stripped. A gap fill layer is thereafter deposited over the dielectric layer to fill the deep trench. Other objects, advantages, and novel features of the claimed invention will become more clearly and readily apparent from the following detailed description when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 6190974 (2001-02-01), Wang
patent: 6251732 (2001-06-01), Hsu
patent: 6621129 (2003-09-01), Lin et al.
Chen Chih-Hung
Cheng An-Ru
Liu Kwo-Jen
Faraday Technology Corp.
Hsu Winston
Le Thao P.
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