Semiconductor device manufacturing: process – With measuring or testing – Electrical characteristic sensed
Patent
1997-03-28
1999-05-04
Dutton, Brian
Semiconductor device manufacturing: process
With measuring or testing
Electrical characteristic sensed
G01R 3126, H01L 2166
Patent
active
058997032
ABSTRACT:
Large area chip functionality is tested at an intermediate level in the manufacturing process. A process sequence is implemented in which a layer of insulator material is deposited over the chip. This layer is then processed to selectively open areas over existing vias which are to be used for chip level testing. The other vias remain covered with insulator. A sacrificial metal level is then deposited on the insulator layer and patterned to create adequately large test pad areas connected to exposed vias. This metal layer and the insulator layer covering the other buried vias are removed after testing to re-establish the full via set. As an extension to this basic test process, test circuits can be formed around or beside the chip to be tested in the kerf areas separating the chip from other chips on the semiconductor wafer. Connections to the test circuits is with a sacrificial metal layer over an insulator layer. The sacrificial metal layer and insulator layer are removed after testing. The test circuits are scribed off in the process of separating the chips after back end of line processing is completed.
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Kalter Howard L.
Pogge H. Bernhard
Prokop George S.
Wheater Donald L.
Ahsan Aziz M.
Dutton Brian
International Business Machines - Corporation
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