Method for burst mode, bit line charge transfer and memory...

Static information storage and retrieval – Read/write circuit – Precharge

Reexamination Certificate

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C365S185250, C365S189150, C365S204000, C365S233170, C365S233180

Reexamination Certificate

active

07463539

ABSTRACT:
A memory device operates according to a method for reading includes pre-charging a first set of selected bit lines to a pre-charge voltage and sensing data from the cells coupled to the first set of selected bit lines. Then, residual charge is transferred from the first set of selected bit lines to corresponding members of a second set of selected bit lines. The second set of selected bit lines, having an initial charge transferred from the first set, is then pre-charged to the pre-charge voltage. The data from the cells coupled to the second set of selected bit lines it is then sensed. In embodiments described herein, the read operation occurs in a burst read mode, where a volume of data having consecutive addresses is read.

REFERENCES:
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patent: 6498751 (2002-12-01), Ordonez et al.
patent: 7082061 (2006-07-01), Chou et al.
patent: 2006/0146623 (2006-07-01), Mizuno et al.
patent: 2006/0274589 (2006-12-01), Suh
Le et al. “Virtual-Ground Sensing Techniques for a 49-na/200-MHz Access Time 1.9-V 256-Mb 2-Bit-per-Cell Flash Memory,” IEEE Journal of Solid-State Circuits, vol. 39, No. 11, 2014-2023.
Pathak et al., “A 1.8V 64Mb 100MHz Flexible Read While Write Flash Memory,” 2001 IEEE Int'l Solid-State Circuits Conf. 4 pages.

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