Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2001-09-17
2003-04-01
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S718000, C714S732000, C714S739000, C365S201000
Reexamination Certificate
active
06543019
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a method and a corresponding device for the built-in self test of an electronic circuit which contains both a combinatorial logic and a memory.
Hitherto, the hardware expenditure for the test logic of a built-in self test (BIST) has been extremely large in electronic circuits which contain both a combinatorial logic and memory elements (RAM and/or ROM). This is due to the fact that the combinatorial logic and the memories contained in the same circuit were always tested separately from one another in the prior art. Both a self test circuit for testing the logic and a separate self test circuit which tested only the memory part have therefore been provided according to the prior art. Of course, this involved a considerably higher degree of expenditure on circuitry, and usually also a longer testing time.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method and a device for built-in self testing of electronic circuits which contain both a combinatorial logic and a memory, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which renders it possible to implement this device and this method with considerably less expenditure on hardware, and preferably also to reduce the time required for the self test.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for the built-in self test of an electronic circuit which contains a combinatorial logic and a memory. The method comprises the following steps:
providing a common self test circuit for the logic and the memory of the electronic circuit, the self test circuit having a pseudo-random pattern generator and a signature register connected to the logic and to the memory, and wherein the memory is addressed with a counter;
stimulating the logic with patterns from the pseudo-random pattern generator to simultaneously test the logic and the memory; and
concurrently writing the patterns of the pseudo-random pattern generator to the memory.
In accordance with a further feature of the invention, the self test is controlled with a clock pulse clocking both the counter for addressing the memory and the pseudo-random number generator supplying the input data for the combinatorial logic and for the memory.
The objects of the invention are thus achieved with the common self test circuit that simultaneously tests the logic and the memory.
In this context it is particularly preferred for the self test circuit to comprise a pseudo-random pattern generator which is connected both to the logic and to the memory. In this way, only a single pseudo-random pattern generator is required. It is also advantageous if the control logic for the self test is connected both to the pseudo-random pattern generator and to the counter for addressing the memory.
The outputs of the logic and of the memory are preferably connected to a common signature register. In this way, one signature register is sufficient.
It is particularly preferred here for both the signature register and the pseudo-random pattern generator to be constructed from feed-back shift registers.
Furthermore, the present invention achieves this object by means of a method for the built-in self test of such a circuit, wherein method the logic and the memory are tested simultaneously and largely using the same hardware.
It is particularly preferred here for the self test to be controlled by means of a clock pulse which clocks both a counter for addressing the memory and a pseudo-random pattern generator which supplies the input data both for the combinatorial logic and for the memory.
The output data of the combinatorial logic and of the memory are preferably fed to the signature register wherein this data are compressed. In this way, a single signature register is sufficient for the common self test.
A sequence of the self test which is particularly easy to follow is obtained if the counter determines the address of the memory to which the data of the pseudo-random generator are written.
In accordance with a preferred feature of the invention, the most significant bit of the counter determines whether the memory is written to or the memory is read so that, as the counter increments or decrements, all the memory addresses are first written to and then read. Therefore, if the counter increments, the writing state must correspond to the most significant bit at 0, and the reading state to the most significant bit at 1. If the counter counts backwards (decrements), the most significant bit
1
means writing and the most significant bit
0
means reading.
In accordance with another feature of the invention, the end of the self test is determined when the counter overflows.
Fed-back shift registers are preferably used respectively as the signature register and as the pseudo-random generator.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method and a device for the built-in self test of an electronic circuit, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
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Dirscherl Gerd
Kniffler Oliver
De'cady Albert
Greenberg Laurence A.
Infineon-Technologies AG
Mayback Gregory L.
Stemer Werner H.
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