Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-07-07
2002-07-09
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S624000, C438S634000, C430S317000
Reexamination Certificate
active
06417096
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a method for manufacturing the multi level interconnects of semiconductor devices, and more particularly to avoid photo residue on the dual damascene process.
2. Description of the Prior Art
When semiconductor devices of integrated circuit (IC) become highly integrated, the surface of the chips can be not supplied with enough area to make the interconnects. For matching up the requirement of interconnects increase with Complementary Metal-Oxide-Semiconductor (CMOS) devices shrinks, many designs of the integrated circuit have to use dual damascene method. Moreover, it is using the three-dimensional structure of multi-level interconnects at present in the deep sub-micron region, and inter-metal dielectric (IMD) as the dielectric material which be used to separate from each of the interconnects. A conducting wire which connects up between the upper and the down metal layers is called the via plug in semiconductor industry. In general, if an opening which forms in the dielectric layer exposure to devices of the substrate in interconnects, it is called a via.
According to particular of the process, it will compartmentalize three types, such as the single type, the dual type and the self-aligned type. The damascene is that etch the trench of interconnects in the dielectric, and then fill the metal as interconnect. This method can introduce metal that is difficult etched into the semiconductor without etching in the interconnect process. Therefore, this invention is the best method of the interconnect process in the sub-quarter micron.
Conventional dual damascene is as shown in
FIG. 1A
, first of all, a dielectric
12
is formed over on the substrate
10
, and a etching stop layer
14
is formed over on the dielectric
12
, then a dielectric
16
is formed over on the etching stop layer
14
. And then a photoresist layer
18
is formed on the dielectric
16
, then the photoresist layer
18
is patterned as a deep pattern area. As show in
FIG. 1B
, dry etching of the deep patterns is proceeded by means of the photoresist layer
18
as a mask, then punch through the dielectric
16
, etching stop layer
14
and the dielectric
12
, and forming a via hole, then remove the photoresist layer
18
. As show in
FIG. 1C
, a photoresist layer
22
is formed on the dielectric
16
by deposition, and it is defined to form a shallow pattern area, and the partial surface of the via
20
and the dielectric
16
are exposed, likewise, the horizontal size of the shallow patterns is large more then one of the deep patterns. As show in
FIG. 1D
, dry etching of the shallow patterns is proceed by means of the photoresist layer
22
as a mask, and exposed partial surface of the dielectric
16
is removed to form a trench
24
having large horizontal size to take advantage of etching stop layer
14
is as a etching terminal point. As show in
FIG. 1E
, the photoresist layer
22
is removed to form the opening of the damascene
20
,
24
. Final, proceed a interconnect process, since the above processes are well known in the prior art, which are not the focus of the present invention, hence will not be described in greater details.
The skill of the dual damascene is a method for forming the via and the interconnects. For the dual damascene application, the material of the dielectric layer general use low-K material. The low-K dielectric material is popular to apply copper (Cu) dual damascene process to decrease resistance capacitance (RC) delay time of interconnect material below 0.13 um generation, the cause of the resistance capacitance (RC) delay time is due to result the parasitic capacitance from the inter-metal dielectric layer. But the residue is found on low-K material (such as coral, black-diamond, etc) surface and in via side wall after develop because some low-K material was reactive with photo resist. The residue would induce fence in via or big defect on low-K material surface after etch. The issue would induce short between metal.
In the dual damascene process, the organic bottom anti-reflection coating, polymer as gap-filling material and deposition protect material was applied this process which increase cost and complex process. Some low-K material still having fence or residue after using gap-filling material, and deposition protect material is difficult to find without increase K value.
In conventional dual damascene process, the photoresist is put on the surface of the low-K material before expose via (via first process) or trench (trench first process). The residue will be observed on exposure area, as shown in FIG.
4
A. The root cause of photo residue
400
is combined several chemical reaction between low-K material and photoresist.
The photoresist residue
510
will remain on the sidewalls of the trench after conventional pattern process, as shown in FIG.
5
A. Thereby, the fence
520
that affects the quality of the process will be happened after trench etching as shown in FIG.
5
B.
In accordance with the above description, a new and improved method for avoiding photo residue on the dual damascene process is therefore necessary, so as to raise the yield and quality of the follow-up process.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for avoiding photo residue on the dual damascene process that substantially overcomes drawbacks of above mention problems arose from the conventional methods.
Accordingly, it is an object of the present invention to provide a method for avoiding photo residue on the dual damascene process, the present invention deal the surface of the low-K dielectric material that has been exposed with acid, the surface that has been dealt with acid will not react with the photoresist layer. Namely, the cause of the residue can be avoided by acid treatment before the trench pattern, so as to solve the above issue.
The other object of the present invention is that provide a method for avoiding photo residue on the dual damascene process, the present invention deal the surface of the low-K dielectric material that has been exposed with acid, so as to prevent the low-K dielectric layer is destroyed while the photoresist layer and photo residue are being removed. Thus, the method of the present invention is effective in raising quality of the process.
Another object of the present invention is that provide a method for avoiding photo residue on the dual damascene process, and the present method is a simply process that is applied to solve above issue than gap-filling material on trench or deposit protect material on trench and via. The method is lowest cost than add gap-filling material and deposit protect material. Thus, the method of the present invention is easily and to conform to the economic effect, and it is suitable for use in the sub micron.
A further object of the present invention is that provide a acid solvent, the acid solvent is dilute solution like as Lewis acid (such as H
2
SO
4
, DHF, HCL) that is easy to induce H
+
ions in solution.
In accordance with the present invention, a method for avoiding photo residue on the dual damascene process is disclosed. In one embodiment of the present invention, a substrate is provided. A first dielectric layer is formed over the substrate by deposition. Etching stop layer and a second dielectric layer are formed in turn over the first dielectric by deposition. Next, the second dielectric layer is dealt with Lewis acid. Then, a first photoresist layer is defined and formed over the second dielectric layer that is treated with Lewis acid. And then dry etching is carried out by means of the first photoresist layer as the mask, and punch through in turn the second dielectric layer, the etch stop layer and the first dielectric layer to form a via hole. Then, the first photoresist layer is removed. The surface of the second dielectric layer and the via hole are treated with Lewis acid. Subsequently, the second photoresist layer is formed on the second dielectric layer, and the
Chang Sheng-Yueh
Chen Anseime
Maeda Jun
Wang Sung-Hsiung
Lytle Craig P.
Powell Goldstein Frazer & Murphy LLP
Smith Matthew
United Microelectronics Corp.
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