Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-09-15
2002-01-22
Whitehead, Jr., Carl (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06341365
ABSTRACT:
FIELD OF THE INVENTION
The following invention relates generally to signal transmission in Very Large Scale Integration/Ultra Large Scale Integration (VLSI/ULSI) systems and specifically to repeater device placement process and method for improving signal transmission performance and electrical integrity.
TRADEMARKS
S/390 and IBM are registered trademarks of International Business Machines Corporation, Armonk, N.Y., U.S.A. and Lotus is a registered trademark of its subsidiary Lotus Development Corporation, an independent subsidiary of International Business Machines Corporation, Armonk, N.Y. Other names may be registered trademarks or product names of International Business Machines Corporation or other companies.
BACKGROUND
A typical problem in implementing high performance in semiconductor circuits (chips) is accurately transmitting a signal along the length of a metal connector (called a net) traversing relatively long distances on the chips. An additional problem is maintaining an acceptable signal voltage transition rate along the length of the net. The net can be a piece or strip of metal (e.g., copper) acting as a transmission medium and traversing the length or nearly the length of the chip. This signal voltage transition rate is also called a slew rate or signal slew rate.
A poor signal slew rate has several detrimental effects which impact the overall performance and electrical integrity of the digital circuit. The performance of a digital circuit is degraded by a poor signal slew rate in several ways: the propagation delay of a signal with poor slew rate is increased and the propagation delay of the next stage in the circuit is also degraded by the slower switching rate at the input. The electrical integrity of the circuit is adversely effected since a poor slew rate at the input of a circuit is more susceptible to being effected by electrical noise which can come in the form of coupled line (or wire) noise or power supply noise. A solution to poor signal slew rates in the interconnect of digital circuits is to provide one or more buffers (or repeaters) along the interconnect wire(s) to allow repowering of the electrical signals which in effect increases the slew rate and reduces the switching time. In a typical high performance VLSI circuit design implementation the analysis of the performance of the system required to determine the slew rate of each signal is performed once the overall floorplan and placement of the devices is known. Once the floorplan and device placement is known the parasitic loading (resistive, capacitive and inductive characteristics of the circuit interconnect) can be evaluated and used as input to estimate or simulate performance. Once the performance of each net in the system is evaluated the nets with poor slew rates can be identified. Once these nets are identified the corrective action of buffer insertion can be applied. What is required is a means for placement of the repowering buffers to correct poor signal slew rates within a given digital VLSI circuit design with a known floorplan and device placement.
A typical net may have a length on the order of 17 millimeters, which is the length of a typical chip, and comprise a number of different layers, such as 6 layers of metal, all insulated from one another vertically and horizontally. The width of a net is on the order of less than one micron.
The signal is typically either a low or high voltage signal. The circuit element transmitting the signal is called the driver. The circuit element receiving the signal is called a receiving device or receiver. The net transmits the signal from the driver to the receiving device. The trouble is that the longer the length of the net between the driver and the receiving device, the more difficult it is to recapture an accurate, sharp signal at the receiving end, and the more difficult it is to have an unaffected slew rate for propagation of the electrical signal.
In a typical chip, the clock rate is about 1 nanosecond. A good slew rate is considered to be approximately 40% or less than the clock rate, or 400 picoseconds or less. The longer the length of the net, the more adversely the net is impacted.
If the propagation delay is slow, then the propagation delay for the receiving circuit is degraded. Also, if a signal propagates slowly, then the net is susceptible to electrical noise caused by capacitive coupling with neighboring wires, or other parasitic effects.
For this reason, repeaters are provided along the path of the net to regenerate the signal. The repeater is called a buffer device.
The ideal location for the repeater is at a midpoint between the driver and the receiving device. Unfortunately, this midpoint is often occupied by other devices on the chip, called predefined blockages, because their floor space on the chip has been predefined by designers. Finding the midpoint is not a trivial task, because there may be more than one receiving device, to which the signal on the net propagates. Manually searching for an optimal point to place the repeater is disadvantageous because it is time consuming, considering the number of repeaters that may be required.
What is required is an automatic method for providing an optimal point in which to place the repeater along a net traversing a long distance relative to a chip.
SUMMARY OF THE INVENTION
The present invention is directed to a method, and a system for using the method, for placing a semiconductor circuit device between a driver and one or more receivers on the floor space of a chip.
The method includes the steps of: determining respective distances between the driver and each of the one or more receivers; determining a shortest of the distances; determining midpoint along the shortest distance; determining whether the midpoint is predesignated to the floor space of one or more blocking semiconductor circuit devices; placing the repeater at the midpoint if the midpoint is not predesignated to the one or more blocking semiconductor circuit devices; and applying a backoff algorithm to incrementally back away from the midpoint to an optimal location, and placing the repeater at the optimal location, if the midpoint is predesignated to the one or more blocking semiconductor circuit devices.
The method can also include the steps of: determining whether the to be placed semiconductor circuit device can be placed at a set of incremental locations located along one or more axes away from the midpoint; and placing the to be placed semiconductor circuit device at one of the one or more acceptable incremental locations. The step of determining the set of incremental locations can be performed in a spiral pattern away from the midpoint. This can include determining a subset of locations of the set of incremental locations positioned outside the floor space of the blocking semiconductor devices; and placing the semiconductor device at one of the subset of locations located along a shortest path between the driver and the receiver located closest to the driver.
The semiconductor circuit device to be placed can be a repeater along the path of a net. The driver can be a semiconductor device. The driver can be a group of semiconductor devices. The one or more receivers can be one or more semiconductor devices. The one or more receivers can be one or more groups of semiconductor devices.
The repeater device can include: two pairs of circuit elements, each pair comprising an n-doped field effect transistor (NFET) and p-doped field effect transistor (PFET) coupled together, wherein the pairs are coupled together in a non-inverting circuit.
REFERENCES:
patent: 6030110 (2000-02-01), Scepanovic et al.
patent: 6025571 (2001-03-01), Camporese et al.
Cao, et al., Effects of Global Interconnect Optmizations on Performance Estimation of Deep Submicron Design; IEEE Conference on CAD; pp. 56-61; 2000.*
Shah, et al., “Wiresizing with Buffer Placement and Sizing for Power-Delay Tradeoffs”; Ninth International Conference on VLSI Design; pp. 346-351; 1996.*
Kahng, et al., “Interconnect Otimization Strategies for High-Per
Camporese Peter J.
Dwyer Robert P.
Augspurger Lynn
Cantor & Colburn LLP
Jr. Carl Whitehead
Speight Jibreel
LandOfFree
Method for automating the placement of a repeater device in... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for automating the placement of a repeater device in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for automating the placement of a repeater device in... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2831469