Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-09-04
2004-11-30
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06826743
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to overlay alignment of a stepper in the fabrication of a semiconductor device. More particularly, the present invention relates to an overlay correction method for aligning semiconductor wafers that are exposed by a stepper.
2. Description of the Related Art
In order to fabricate semiconductor devices, silicon wafers typically undergo various processes, such as cleaning, diffusion, photoresist coating, exposure, developing, etching, ion-implantation, and the like. Each one of these processes requires a corresponding piece of equipment. For an exposure process, a stepper is used to expose photoresists that have been coated on the wafers using light from a light source, so that the wafers may be patterned during subsequent developing and etching processes.
In the exposure process, a predetermined number of wafers that have been coated with a photoresist are loaded into a carrier, which is then loaded on a table in the stepper. Since the wafers are typically exposed one layer at a time in the stepper, a fetch arm enters the carrier to select and grip one wafer to initiate the exposure process. Next, the table displaces by one pitch, thereby extracting one wafer from the carrier. As the wafer is removed from the carrier, a slider moves to receive the wafer and the wafer in the slider is thus transferred to a position where the wafer is to be exposed. The stepper performs an alignment process on the wafer and then steps through an exposure process at every unit chip location on a wafer to form a predetermined pattern on the wafer. Since the wafer needs to be accurately exposed in order to form a highly integrated chip, the wafers require accurate and proper alignment.
A technique for correcting an overlay of a wafer in order to align a wafer accurately has been developed. In this conventional technique, a test wafer from a particular processing batch or lot is exposed, and a test exposure result is fed back to correct any misalignment of the test wafer. This alignment correction is stored and later used for aligning each wafer in that particular processing batch or lot.
FIG. 1
illustrates a diagram of a conventional system for correcting an overlay of a wafer using such a technique. The conventional system of
FIG. 1
includes a stepper
10
for performing a photolithographic process on a semiconductor device, an overlay measuring part
12
for measuring three sets of offset wafers during the exposure process in the stepper to create overlay characterization data, an interfacing part
14
connected to the stepper
10
and the overlay measuring part
12
in order to interface data signals that are input/output through a data bus
20
, a data server
16
and an operator interface server
18
, each of which is connected to the data bus
20
.
After the operator interface server
18
is input with various parameters required for the exposure process, associated input parameters are transferred to the interface part
14
via the data bus
20
. The input parameters are then input to the stepper
10
, which performs an exposure process according to the input parameters. The stepper
10
records and transmits product related process information, such as product title and type of the practically processed semiconductor device, recorded data, process parameters such as information regarding the reticule, or reticules, that were employed during an exposure process, a lot number, and the like to the data server
16
through the interfacing part
14
and the data bus
20
. Simultaneously, the overlay measuring part
12
detects and records overlay data of wafers that are exposed in the stepper
10
in order to transmit the result to the data server
16
through the interface part
14
and the data bus
20
. The data server
16
receives the overlay data that was measured in the overlay measuring part
12
during an exposure process in order to detect any misalignment and calculate error correction values for the overlay according to the following set of equations, hereinafter referred to as formula I:
X
(
k
)=
X
_stepper(
k
)−
X
—
ffwd
(
k
)−
X
—
kla
(
k
) [1]
Z
(
m
)=
w
1
*X
(
k
31 1)+
w
2*
X
(
k
−2)+
w
3
*X
(
k−
3
) [2]
X
_stepper(
k
)=
X
—
ffwd
(
k
)+
Z
(
m
) [3]
wherein X(k) is a current overlay alignment value; X_stepper(k) is an error correction value of the overlay; X_ffwd(k) is a reference value for wafer alignment; X_kla(k) is an overlay-measured value; Z(m) is a weighted average value for a latest three lots, w1, w2, w3 are the weighted values; X(k−1) is a latest overlay alignment value; X(k−2) is a second latest overlay alignment value; and X(k−3) is a third latest overlay alignment value.
The overlay error correction value X_stepper(k) in formula I is calculated by summing the weighted average value (w1:w2:w3→5:3:2) of the latest three lots measured in a same history and the reference value X_ffwd(k) for wafer alignment of a lot to be processed. The overlay error correction value X_stepper(k) is applied to the operator interface server
18
and provided as overlay data for an exposure process to be performed for a subsequent lot. At this time, the data server
16
divides and stores overlay data according to a grouping criteria, such as a same load of the same stepper, a same pattern of the same lot, a same device, and the like. Such division of the overlay data by the data server
16
results in forming groups of same types of overlay data, thereby maintaining consistency in data.
Since the conventional overlay correction method as described above is performed by summing only the weighted average value of three lots that are within a range bounded by the latest data and the previous data and the reference value for the wafer alignment of a lot to be processed, variances in equipment characteristics with respect to time are not considered, thereby causing frequent specification failures. Further, there is a disadvantage in that a sample process is required due to a lack of historical data in a production line involving Job Shop Type Production and Small Batch Production.
SUMMARY OF THE INVENTION
In an effort to solve the problems as described above, it is a feature of an embodiment of the present invention to provide, in semiconductor fabricating stepper equipment, a semiconductor wafer overlay correction method for correcting a positioning of an overlay of a semiconductor wafer that incorporates variances in equipment characteristics with respect to time.
It is another feature of an embodiment of the present invention to provide a semiconductor wafer overlay correction method that minimizes initialization time for sampling and exchanging wafers used for calibration of an exposure process for a production line for Job Shop Type Production and Small Batch Production, thereby increasing productivity.
According to an aspect of the present invention, a wafer overlay correction method for an exposure process in a semiconductor fabricating stepper includes measuring an overlay error correction value of a semiconductor wafer that is exposed by the stepper, calculating an overlay error correction value by summing the measured overlay error correction value, a variation in the stepper that is obtained through an empirical characterization of input changes, and a weighted value obtained from a predetermined plurality of lots, and providing the calculated overlay error correction value to the stepper to control an exposure process of a subsequent wafer lot. The predetermined plurality of wafer lots may preferably include the latest ten lots measured in the same history data.
These and other features of the present invention will be readily apparent to those of ordinary skill in the art upon review of the detailed description that follows.
REFERENCES:
patent: 4910679 (1990-03-01), Takahashi et al.
patent: 5711843 (1998-01-01), Jahns
patent: 5989762 (1999-11-01), Ta
Cho Bong-Su
Kang Hyun-Tae
Park Chan-Hoon
Dinh Paul
Lee & Sterba, P.C.
Samsung Electronics Co,. Ltd.
Siek Vuthe
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