Method for automatic adjustment of timing of double data...

Details Method for automatic adjustment of timing of double data... Method for automatic adjustment of timing of double data...

2006-10-31

2009-12-22

Thai, Tuan V (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S104000, C711S105000, C711S168000, C711S100000, C711S111000, C711S112000, C365S230030, C365S233100, C365S233130, C710S022000, C710S025000, C710S033000, C710S034000, C710S035000, C710S058000, C710S059000, C710S060000, C710S061000

Reexamination Certificate

active

07636828

ABSTRACT:
Timing of a write and read strobes for a memory having a double data rate (DDR) interface are automatically adjusted using write-read operations. A first and a second value of the write and read strobes are determined for a first write-read operation having the read data match the write data. A second write-read operation is performed for each of a plurality of third values for the write strobe at the second value for the read strobe set. A center of the third values having the read data match the write data is determined. A third write-read operation is performed for each of a plurality of fifth values for the read strobe at the fourth value of the write strobe. A center of the fifth values having the read data match the write data is determined. The timing of the write and read strobes are set to the centers.

REFERENCES:
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patent: 6664838 (2003-12-01), Talledo
patent: 6889334 (2005-05-01), Magro et al.
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patent: 2005/0057978 (2005-03-01), Stubbs
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