Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-07-29
2008-09-23
Louis-Jacques, Jacques (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S735000
Reexamination Certificate
active
07428679
ABSTRACT:
A test head performs at-speed testing of high serial pin count gigabit per second (GBPS) devices. The test head includes a device under test (DUT) coupled to a first portion of the test head and a rider board coupled to the DUT. The rider board includes a first signal path including switching matrices coupled to the DUT, a second signal path including bit error rate testing (BERT) engines, each of the BERT engines being coupled to each other, corresponding ones of the switching matrices, and to the DUT, and a third signal path including Ethernet testing circuits coupled to the DUT. The BERT engines allow for routing of a test signal from any of the switching matrices to any other switching matrix (e.g., between non-adjacent switching matrices).
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Broadcom Corporation
Gandhi Dipakkumar
Sterne Kessler Goldstein & Fox PLLC
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