Method for at-speed testing of memory interface using scan

Details Method for at-speed testing of memory interface using scan Method for at-speed testing of memory interface using scan

2006-05-24

2009-11-10

Trimmings, John P (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S005110, C714S025000, C714S030000, C714S718000, C714S723000, C714S720000, C714S726000, C714S727000, C714S729000, C714S730000, C714S732000, C714S733000, C714S734000, C714S736000, C714S742000, C714S743000, C365S201000

Reexamination Certificate

active

07617425

ABSTRACT:
A method and a circuit of testing of a memory interface associated with an embedded memory in a semiconductor circuit involves writing to two memory locations in succession; reading the two memory locations in succession in the same order in which the two memory locations were written; capturing output data from the memory interface; and analyzing captured output data to determine whether said captured output data corresponds to expected data.

REFERENCES:
patent: 6715117 (2004-03-01), Mangyo et al.
patent: 6876591 (2005-04-01), Gappisch et al.
patent: 7222272 (2007-05-01), Takazawa et al.
patent: 7287202 (2007-10-01), Simeral et al.
patent: 7370249 (2008-05-01), Bao et al.
patent: 2006/0218452 (2006-09-01), Njinda et al.

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