Static information storage and retrieval – Read/write circuit – Including signal comparison
Patent
1988-12-05
1990-06-12
Shaw, Gareth D.
Static information storage and retrieval
Read/write circuit
Including signal comparison
3642422, 3642426, 3649414, 36493701, 365221, G06F 1300
Patent
active
049339010
ABSTRACT:
An arbiter (52) is operable to supply an up/down signal (11) and a clock signal (13) to an up/down counter (10) so that the up/down counter (10) can count the difference between read requests (54) and write requests (56) experienced by an associated FIFO memory.
The arbiter (52) is operable to receive asynchronous read and write requests (54, 56) that are closely spaced in time or appear simultaneously, and to store the read request in a read latch (104) and the write request in a write latch (92). A decision circuit (62) is operable to determine priority between the read and write requests, and processes the request that is awarded priority. Once the first priority request has been processed, the stored non-priority request is then processed.
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patent: 4222102 (1980-09-01), Jansen et al.
patent: 4281381 (1981-07-01), Ahuja et al.
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patent: 4792926 (1988-12-01), Roberts
patent: 4803681 (1989-02-01), Takahashi
patent: 4805106 (1989-02-01), Pfeifer
patent: 4815039 (1989-03-01), Tai et al.
Chiu Edison
Tai Jy-Der
Barndt B. Peter
Comfort James T.
Ray Gopal C.
Sharp Melvin
Shaw Gareth D.
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