Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-09-24
2004-04-20
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06725433
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to integrated circuits and, more particularly, to a method for testing interconnects to assess the effect of reservoir size on Blech effect.
BACKGROUND ART
Reliability is a major concern regarding integrated circuits. One particular area of concern is electromigration. As device features for transistors become smaller and operating speeds increase, the current density in a transistor's metal lines has increased. The increased current densities often lead to device failures, such as failures due to electromigration.
It has been well established that for aluminum straight line via-to-via interconnect structures, there exists a critical current density and length product (jL
crit
), below which electromigration ceases and the interconnect is considered “immortal” due to a balance between the electron wind force and the opposing back stress force. This effect is known as the Blech effect. The concept of jL
crit
has more recently been reported for copper interconnects.
For example,
FIG. 1A
illustrates a top view of an exemplary interconnect
100
with contacts
110
and
120
. The contacts
110
and
120
may represent vias that connect interconnect
100
to other metal layers and electrons may flow from contact
110
to contact
120
. Referring to
FIG. 1A
, when the electron wind force caused by atom flux and the opposing back stress force are equal, interconnect
100
is considered immortal. That is, interconnect
100
will not experience electromigration failure.
This phenomenon implies that the tensile stress due to electromigration is maximized at the no-flux cathode line end and decreases linearly toward the no-flux anode line end. When a balance between electron wind and back stress forces is achieved, a steady-state profile results. For example,
FIG. 1B
is a graph illustrating the stress profile of the interconnect
100
. Referring to
FIG. 1B
, the stress profile is linear with a maximum stress value (&sgr;) at the cathode no-flux line end.
The increased reliability of short lines at a given current density has been well studied for straight via-to-via structures with minimal reservoirs at the line ends. The reservoir is the area at the line end that surrounds the compact/via connection point. In conventional chip reliability assessment, this increased reliability for short lines is routinely considered when assessing full chip reliability.
It has also been established that increasing the reservoir area for long lines (i.e., lines in which jL>>jL
crit
) decreases stress on the interconnect caused by electromigration. Thereof, increasing the reservoir size has conventionally been considered a way to increase the median time to failure (MTF) for long interconnects.
The relationship, however, between back stress effects and line ends with significant reservoirs is not well understood and is not considered when assessing circuit reliability. In other words, conventional chip reliability assessments do not consider how the back stress for short lines is affected by the size of a reservoir. This could lead to overly optimistic reliability assessments.
DISCLOSURE OF THE INVENTION
There exists a need for a methodology that assesses the effect of reservoir size on the Blech effect.
These and other needs are met by the present invention, where the relationship between jL
crit
and reservoir area at line ends are taken into consideration by testing interconnect structures with varying reservoir areas. The test results may then be used to more realistically assess chip reliability.
Additional advantages and other features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The advantages and features of the invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method for testing interconnect structures. The method includes forming a plurality of interconnects, where each of the interconnects has two ends with a contact and a reservoir located at each of the ends. Each of the interconnects also has the same length and a different reservoir size. The method also includes supplying a voltage to each of the plurality of interconnects and measuring stress values for each of the respective interconnects. The method further includes determining a relationship between reservoir size and jL
crit
, where jL
crit
represents a current density (j) and interconnect length (L) product below which an interconnect is considered to be immortal.
According to another aspect of the invention, a method for testing a plurality of interconnects is provided. Each of the interconnects includes a via located at each end of the interconnect and each of the interconnects has the same length and a different reservoir sized Each of the interconnects also has a theoretical current density and length product (jL
crit
) value, below which the interconnect is considered immortal. The method includes supplying a voltage to a first one of the vias for each of the respective interconnects, where the voltage results in a first current density j on each of the interconnects such that jL for a first one of the interconnects is below its jL
crit
value. The method also includes measuring stress values for each of the respective interconnects and determining that at least one of the plurality of interconnects is not immortal at the first current density.
According to a further aspect of the invention a method of analyzing a plurality of interconnects is provided. Each interconnect has the same length (L) and a reservoir located at each-end of the interconnect, with each reservoir having a different size. The method includes applying a voltage to each of the interconnects such that a current density (j) on each of the interconnects is achieved, where jL for a first one of the interconnects is less than a theoretical jL
crit
value and the first interconnect is considered immortal. The method also includes measuring stress values for each of the plurality of interconnects and estimating a median time to failure for each of the plurality of interconnects based on the measured stress values.
REFERENCES:
patent: 5506450 (1996-04-01), Lee et al.
patent: 5614764 (1997-03-01), Baerg et al.
patent: 5900735 (1999-05-01), Yamamoto
patent: 6037795 (2000-03-01), Filippi et al.
patent: 6349401 (2002-02-01), Tamaki
patent: 6417572 (2002-07-01), Chidambarrao et al.
patent: 2003/0226121 (2003-12-01), Yokogawa
Hieu V. Nguyen et al.; Modelling of the Reservoir Effect on Electromigration Lifetime; Proceedings of 8thIPFA; 2001, Singapore; pp. 169-173.
S. Thrasher et al.; Blech Effect in Single-Inlaid Cu Interconnects; IITC Proceedings; 2001; pp. 177-179.
Hau-Riege Christine
Marathe Amit
Dinh Paul
Harrity & Snyder LLP
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