Method for arranging a memory cell array in semiconductor memory

Details Method for arranging a memory cell array in semiconductor memory Method for arranging a memory cell array in semiconductor memory

1995-12-28

1998-08-04

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Bad bit

36523006, G11C 700

Patent

active

057904642

ABSTRACT:
A method of arranging a memory cell array in a semiconductor memory device, comprising the steps of dividing the memory cell array into a plurality of memory cell array areas having equal size, providing within the memory cell array a plurality of sub-normal memory cell arrays and at least one redundant memory cell array, arranging the plurality of sub-normal memory cell arrays and the at least one redundant memory cell array into the plurality of memory cell array areas, and arranging a plurality of sub-normal word line drivers, such that each sub-normal word line driver is adjacent to one of the plurality of memory cell array areas.

REFERENCES:
patent: 5255234 (1993-10-01), Seok
patent: 5459690 (1995-10-01), Rieger et al.
patent: 5617364 (1997-04-01), Hatakeyama

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