Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1997-03-31
1999-10-19
Beausoliel, Jr., Robert W.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
714728, G01R 3128
Patent
active
059681942
ABSTRACT:
A method and apparatus for using weighted random patterns in a partial scan test. A computer generates deterministic patterns on the partial scan design. Deterministic patterns that have the same number of capture clocks between adjacent scan loads are grouped together into pattern groups. A computer then determines a set of weights corresponding to each of the pattern groups. A tester then uses these weights as a filter to weighted random test patterns and applies these filtered weighted random test patterns along with the appropriate number of capture clock pulses to a device under test.
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Gollakota Naga
Parvathala Praveen
Wu David
Beausoliel, Jr. Robert W.
Intel Corporation
Iqbal Nadeem
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