Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-09-11
2003-10-21
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S795000, C438S952000
Reexamination Certificate
active
06635541
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is directed to a method for annealing a substrate with radiant energy using a partial absorber layer. The invention is also directed to an integrated device(s) or circuit(s) made by such method. The substrate can be composed of silicon, gallium arsenide, or other semiconductor species, or can include an insulative material with a relatively thin-film of semiconductor material formed thereon. The method can be used to anneal or activate an integrated device(s) or circuit(s) formed in the substrate. Such integrated devices can include active devices such as transistors or diodes, or passive devices such as resistors or capacitors. For example, the apparatus and method can be used to anneal a substrate to obtain a relatively high crystalline state therein, or to activate the substrate to incorporate dopant atoms into the substrate's crystalline lattice, to achieve proper electrical performance of the integrated device(s).
2. Description of the Related Art
The ongoing reduction in scale of integrated devices formed in semiconductor substrates requires relatively shallow source/drain junctions for proper electrical performance. Laser thermal processing (LTP), which melts and re-solidifies a thin surface layer of semiconductor substrate using a pulsed laser radiation, is a promising technology for annealing shallow junctions. However, two issues must be resolved for successful integration of LTP into a process for forming integrated devices. First, the gate must be prevented from deforming upon treatment with radiant energy. Second, due to interference effects with radiant energy, the heating of the substrate underneath the field isolation regions can be greater than the heating in the source/drain regions. Such interference effects can lead to undesirable melting of the substrate beneath the field isolation regions. It would be desirable to overcome, these problems to permit effective use of LTP to anneal integrated device(s) formed in a substrate. In U.S. Pat. No. 5,956,603 issued Sep. 21, 1999 to Somit Talwar, et al., a full absorber approach was disclosed where a highly radiation-absorbent layer was deposited on top of the integrated device(s). This absorber layer blocks the radiation from traveling through the field isolation regions, and also preserves the gate physical integrity. A new problem arises with the introduction of a full absorber layer due to differential thermal properties at different regions of integrated device(s). The thermal conductivity of silicon dioxide, which is the common material for field isolation, is significantly lower than that of silicon substrate. As a result, the absorber layer is much hotter in temperature over field isolation regions than over source/drain regions. In fact, the surface temperature of the absorber in field isolation regions can even exceed the melting temperature of the absorber material, leading to undesirable surface damage or ablation.
SUMMARY OF THE INVENTION
The present invention methods and apparatus overcome the above-stated problems to permit effective use of radiant energy to anneal integrated device(s) formed in a substrate. A method of the invention comprises forming a partial absorber layer (PAL) over at least one integrated transistor device formed on a semiconductor substrate. The method also comprises exposing the PAL to radiant energy. The radiant energy can include a first portion that passes through the PAL and is absorbed in the source and drain regions adjacent a gate region of the integrated transistor device. The first portion of radiant energy can also be absorbed in the semiconductor substrate underneath the field isolation regions of the integrated device. The radiant energy can also include a second portion of radiant energy that is absorbed by the PAL and is thermally conducted from the PAL to the source and drain regions. The first and second portions of the radiant energy can be of sufficient energy to melt the source and drain regions to anneal the junctions of the integrated device. The PAL can be formed so that the first portion of radiant energy traveling to the substrate underneath the field isolation regions is sufficiently reduced in fluence to prevent melting of the substrate. The PAL can also be formed so that the second portion of radiant energy absorbed by the PAL over the field isolation regions is of insufficient energy to cause ablation or surface damage to the PAL. Accordingly, the source and drain junction regions can be melted for annealing without overheating the PAL or the substrate beneath the field isolation regions.
The material composing the PAL can be selected to be compatible with an integrated circuit manufacturing environment. It can be composed of at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and/or tantalum nitride (TaN). Alternatively, the PAL can be composed of doped spin-on glass. The PAL can be, formed with a stress of less than 5 e
9
dynes per square centimeter to ensure that it will not crack or adversely impact a gate region of the integrated transistor device. The thickness of the PAL can be between one-hundredth (0.01) to three (3) times the optical absorption length of the material composing the PAL at the wavelength of radiant energy used for annealing. The radiant energy used in the exposing can be generated from a laser, for example. The radiant energy fluence can be from five-hundredths (0.05) to one (1) Joule per square centimeter at a wavelength from one-hundred fifty-seven (157) to one-thousand sixty-four (1,064) nanometers. The method can also comprise forming a barrier layer over the substrate. The barrier layer can be situated between the substrate and the PAL. The barrier layer can be used to prevent contamination of the substrate by blocking diffusion of material from the PAL into the substrate. The barrier layer can be composed of silicon dioxide (SiO
2
) and/or silicon nitride (Si
3
N
4
). The barrier layer can be formed using low-temperature oxidation (LTO) or plasma-enhanced chemical vapor deposition (PECVD). The method can also include forming a dielectric layer over the PAL. The dielectric layer reinforces the mechanical strength of PAL under exposure to the radiant energy to preserve the physical integrity of a polysilicon gate layer of the integrated transistor device. This dielectric layer can also be used to add thermal load to the field isolation region so that the surface temperature of PAL in field isolation region can be further reduced to avoid undesirable surface damage or ablation of PAL.
The invention also comprises an article of manufacture including a substrate having an integrated device annealed with radiant energy exposed on a partial absorber layer (PAL) formed on the integrated device. The PAL is situated over a barrier layer that blocks diffusion of atoms from the PAL into the substrate under exposure to radiant energy to prevent contamination of the substrate. The integrated device can be annealed with a dielectric layer formed over the PAL to preserve mechanical strength of the PAL to prevent deformation of a gate layer of the integrated device under exposure to radiant energy. The dielectric layer can also add thermal load over a field isolation region of the integrated device so that the surface temperature of PAL in the field isolation region can be further reduced to avoid undesirable surface damage or ablation of the PAL.
REFERENCES:
patent: 5523262 (1996-06-01), Fair et al.
patent: 5612235 (1997-03-01), Wu et al.
patent: 5956603 (1999-09-01), Talwar et al.
patent: 6090677 (2000-07-01), Burke et al.
patent: 6287927 (2001-09-01), Burke et al.
patent: 6300208 (2001-10-01), Talwar et al.
Gelatos Carol
Talwar Somit
Wang Yun
Jones Allston L.
Niebling John F.
Ultratech Stepper, Inc.
Whitmore Stacy
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