Semiconductor device manufacturing: process – Repair or restoration
Reexamination Certificate
2008-07-29
2008-07-29
Geyer, Scott B. (Department: 2812)
Semiconductor device manufacturing: process
Repair or restoration
C257SE21525
Reexamination Certificate
active
07405088
ABSTRACT:
A failure analysis method according to the invention includes inputting the positions of failures in multiple wafers of an input device; preparing multiple sections in the multiple wafers; calculating feature amounts, which are represented by at least one numerical value representing a distribution of the failures in the multiple wafers, for each of the multiple sections; and representing by a first numerical value, the degree of similarity between the multiple wafers in terms of the feature amounts. Subsequently, the method includes detecting another wafer, which has the first numerical value greater than a predetermined first threshold, for each of the multiple wafers and forming a similar wafer group of multiple wafers with similar distributions of the failures.
REFERENCES:
patent: 5787190 (1998-07-01), Peng et al.
patent: 6545752 (2003-04-01), Swan et al.
patent: 2003/0054573 (2003-03-01), Tanaka et al.
patent: 2003/0096436 (2003-05-01), Satya et al.
patent: 2004/0152250 (2004-08-01), Steele et al.
patent: 2006/0105475 (2006-05-01), Ciplickas et al.
patent: 2006/0142971 (2006-06-01), Reich et al.
patent: 2001-210097 (2001-08-01), None
patent: 2002-269109 (2002-09-01), None
U.S. Patent Application for Hiroshi Matsushita et al., U.S. Appl. No. 10/107,297, filed Mar. 28, 2002.
U.S. Patent Application for Hiroshi Matsushita, U.S. Appl. No. 10/608,155, filed Jun. 30, 2003.
K. Mitsutake, et al., “New Method of Extraction of Systematic Failure Component”, Proc. 10thInt. Symp. Semiconductor Manufacturing, pp. 247-250, (2001).
M. Sugimoto et al., “Characterization Algorithm of Failure Distribution for LSI Yield Improvement”, Proc. 10thInt. Symp. Semiconductor Manufacturing, pp. 275-278, (2001).
K. Nakamae, et al., “Fail Pattern Classification and Analysis System of Memory Fail Bit Maps”, Proc. 4thInt. Conf. Modeling and Simulation of Microsystems, pp. 598-601, (2001).
Notification of Reason for Refusal issued by the Japanese Patent Office, dispatched on May 9, 2006, for Japanese Patent Application No. 2003-076411, and English-language translation thereof.
Kadota Kenichi
Kawabata Kenji
Matsushita Hiroshi
Shioyama Yoshiyuki
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Geyer Scott B.
Kabushiki Kaisha Toshiba
Stevenson Andre′
LandOfFree
Method for analyzing fail bit maps of waters and apparatus... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for analyzing fail bit maps of waters and apparatus..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for analyzing fail bit maps of waters and apparatus... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2814011