Method for analyzing fail bit maps of wafers

Semiconductor device manufacturing: process – With measuring or testing

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257SE21531

Reexamination Certificate

active

07138283

ABSTRACT:
A method of detecting a wafer failure includes extracting the wafer ID of a target wafer in the target lot from the lot ID, extracting the location information of a failure in the target wafer, calculating a to-be-quantified first wafer feature amount for unevenness of a wafer failure distribution, calculating a first lot feature amount for each target lot, extracting a fabrication process for the target lot and a fabrication apparatus, carrying out a significant test for the fabrication apparatus used in each fabrication process, and detecting the fabrication apparatus with a significant difference as a first abnormal apparatus.

REFERENCES:
patent: 6727106 (2004-04-01), Ankutse et al.
patent: 2002/0196969 (2002-12-01), Behkami et al.
patent: 2003/0003608 (2003-01-01), Arikado et al.
patent: 2003/0011376 (2003-01-01), Matsushita et al.
patent: 2003/0019840 (2003-01-01), Smith et al.
patent: 9-180976 (1997-07-01), None
patent: 9-191032 (1997-07-01), None
patent: 10-284564 (1998-10-01), None
patent: 2002-124555 (2002-04-01), None
patent: 2002-289662 (2002-10-01), None
patent: 2002-359266 (2002-12-01), None
K. Mitsutake, et al., IEEE Proc. 10thInt. Symp. Semiconductor Manifacturing, pp. 247-250, “New Method of Extraction of Systematic Failure Component”, 2001.
H. Matsushita, et al., IEEE Transactions on Semiconductor Manufacturing, vol. 15, No. 4, pp. 506-512, “Highly Sensitive Inspection System for Lithography-Related Faults in Agile-Fab-Detecting Algorithm for Monitoring and Evaluation of Yield Impact”, Nov. 2002.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method for analyzing fail bit maps of wafers does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for analyzing fail bit maps of wafers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for analyzing fail bit maps of wafers will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3637036

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.