Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-08-01
2003-12-30
Dang, Phuc T. (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S210000
Reexamination Certificate
active
06670237
ABSTRACT:
BACKGROUND OF INVENTION
1) Field of the Invention
Some embodiments of this invention relates generally to the fabrication of semiconductor devices and particularly to the fabrication of a capacitor in a device and more particularly to a MIM (metal—insulator—metal) capacitor.
2) Description of the Prior Art
In many mixed signal or high frequency RF applications both high performance, high speed capacitors and inductors are required. Low series resistance, low loss, high Q and low (RC) time constants are required in these high frequency applications for high performance. In addition, it is important to fabricate device structures by processes compatible with CMOS processing with AlCu alloys to pure copper in dual damascene structures.
A metal—insulator—metal (MIM) capacitor is used commonly in high performance applications in CMOS technology. Typically, the capacitor has a sandwich structure and can be described as a parallel plate capacitor. The capacitor top metal (CTM) is separated from the capacitor bottom metal (CBM) by a thin insulating layer. Both two parallel plates are conventionally made from Al or AlCu alloys. These metals are patterned and etched needing several photolithography photo masking steps. The thin insulating dielectric layer is usually made from silicon oxide or silicon nitride deposited by chemical vapor deposition (CVD).
The damascene processing is a common method for fabricating planar copper interconnects. Damascene wiring interconnects (and/or studs) are formed by depositing a dielectric layer on a planar surface, patterning it using photolithography and oxide reactive ion etch (RIE), then filling the recesses with conductive metal. The excess metal is removed by chemical mechanical polishing (CMP), while the troughs or channels remain filled with metal. For example, damascene wiring lines can be used to form bit lines in DRAM devices, with processing similar to the formation of W studs in the logic and DRAM devices. In both examples, sputtered Ti/TiN liners, underlying diffusion barriers, have been coated with chemical vapor deposited (CVD) W metal, then polished back to oxide.
In the dual-damascene process, a monolithic stud/wire structure is formed from the repeated patterning of a single thick oxide film followed by metal filling and CMP. First, a relatively thick oxide layer is deposited on a planar surface. The oxide thickness is slightly larger than the desired final thickness of the stud and wire, since a small amount of oxide is removed during CMP. Stud recesses are formed in the oxide using photolithography and RIE that either partially etches through the oxide or traverses the oxide and stops on the underlying metal to be contacted. The wire recesses can then be formed using a separate photolithography step and a timed oxide etching step. If the former stud RIE option is used, the wire etching completes the drilling of the stud holes.
Next, the stud/wire metallization is deposited, then planarized using CMP. The resulting interconnects are produced with fewer process steps than with conventional processing and with the dual damascene process, two layer of metal are formed as one, i.e., wiring line and contact stud vias, avoiding an interface between the layers.
There is a challenge to determine a process that will form capacitors and interconnects using common process steps.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 6,338,999b1(Huse et al.) that shows a process for dual damascenes capacitors.
U.S. Pat. No. 6,329,234b1(Ma et al.) reveals a Cu compatible capacitor process.
U.S. Pat. No. 6,281,134b1(Yeh et al.) shows a process for combining a logic circuit and a capacitor.
U.S. Pat. No. 6,271,084b1(Tu et al.) shows a process for a MIM capacitor using a chemical-mechanical polish (CMP) process.
U.S. Pat. No. 6,025,226(Gambino et al.) shows a method for a capacitor using chemical-mechanical polishing (CMP).
U.S. Pat. No. 6,180,976b1(Roy) shows a thin film capacitor method.
U.S. Pat. No. 6,255,151b1(Fukuda et al.) shows a capacitor method using a chemical-mechanical polish (CMP) step.
SUMMARY OF THE INVENTION
It is an object of an embodiment of the present invention to provide a method for fabricating a capacitor.
It is an object of an embodiment of the present invention to provide a method for fabricating a metal—insulator—metal (MIM) capacitor.
An embodiment of the present invention provides a method of manufacturing a capacitor which is characterized as follows. A capacitor bottom plate and a first metal line are formed over the semiconductor structure. We form a second dielectric layer over the capacitor bottom plate, the first metal line, and a first dielectric layer. Next, we form a top plate opening in the second dielectric layer to at least partially expose the capacitor bottom plate. A capacitor dielectric layer is formed over the capacitor bottom plate and the second dielectric layer. We form a capacitor top plate in the top plate opening. Subsequently, we form a via opening through at least the second dielectric layer and the capacitor dielectric layer over the first metal line to expose a portion of the first metal line. Next, we fill the via opening with a second metal layer to form a via plug. We form a third dielectric layer over the via plug and the capacitor top plate. We form a first trench opening and a second trench opening through the third dielectric layer, the second passivation layer and the third passivation layer. The first trench opening exposes a portion of the capacitor top plate. The second trench opening exposes a portion of the via plug. Next, we form a first trench plug in first trench opening and a second trench plug is the second trench opening. The top plate, the capacitor dielectric and the bottom plate form a capacitor. The via plug and the second trench plug form a interconnect.
Additional objects and advantages of the invention will be set forth in the description that follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of instrumentalities and combinations particularly pointed out in the append claims.
REFERENCES:
patent: 6329234 (2001-12-01), Ma et al.
patent: 6472124 (2002-10-01), Chung
Loh Wye Boon
Ng Chit Hwei
Chartered Semiconductor Manufacturing Ltd.
Dang Phuc T.
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