Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate
Reexamination Certificate
2006-12-26
2010-02-16
Wang, Albert (Department: 2115)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Correction for skew, phase, or rate
C345S204000, C348S537000
Reexamination Certificate
active
07664979
ABSTRACT:
An exemplary method for adjusting clock phase of a monitor includes: setting a reference threshold voltage, when an input voltage of image signals is greater than the reference threshold voltage, a scaler begins to receive clock phases generated by a Phase Locked Loop; dividing the clock phase into a plurality of equal periods, recording a corresponding input voltage at each point dividing two adjacent period, and setting the corresponding input voltage as a threshold voltage of the next period; recording a quantity of the clock pulses in each period; evaluating whether a period of the clock phase is a regular period according to whether the quantity of clock pulse in the period is equal to a reference quantity or not, while the input voltage is generating retardation; and selecting the input voltage of the image signals corresponding to a regular period as a threshold voltage of the scaler.
REFERENCES:
patent: 5561692 (1996-10-01), Maitland et al.
patent: 5936678 (1999-08-01), Hirashima
patent: 6597370 (2003-07-01), Lee
patent: 2007/0200840 (2007-08-01), Clynes et al.
Chung Wei Te
Innolux Display Corp.
Wang Albert
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